Transcript Lecture #27 MOS • LAST TIME: NMOS Electrical Model – Describing the I-V Characteristics – Evaluating the effective resistance R – Switching behavior • TODAY: NMOS.

Lecture #27 MOS
• LAST TIME: NMOS Electrical Model
– Describing the I-V Characteristics
– Evaluating the effective resistance R
– Switching behavior
• TODAY:
NMOS physical structure: W
and L and dox, PMOS
– Transistor Geometry and capacitance
– Scaling of properties with size: ID and C
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EE 42 fall 2004 lecture 27
1
NMOS as a Switch - Summary
We have an equation
for ID in the saturation
region.
ID
ID
D
IDS
G
ID for VGS = maximum (VDD)
N Ch
If VGS = 0.
S
The circuit symbol
VDS
VDD
D
The value of RDN is chosen to
predict the correct timing delay.
Then we can essentially
replace the transistor with the
simple switch model (valid of
course only for predicting
timing delays).
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RDN
G
S
Electrical Model
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2
MOS “Theory”
For simple digital circuit calculations the MOS transistor will be
essentially off (VGS < VT ) or fully turned on (VGS = VDD ), the power
supply voltage).
In the saturation region we describe the variation of ID with VDS with the
empirical equation :
I =I
X (1+ l V )
D
DS
DS
ID
S
VGS
+

G
VGS = VDD
IDS
D
l IDS is slope
iD
+
- VDS
(1/l is intercept with VDS axis)
IDS is the intercept with ID axis
VDS
off
Then we can estimate the effective resistance in terms of l and IDS
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The effective resistance with VGS = VDD
G
The MOS transistor discharges C. (VDD to VDD /2)
D
+
VIN- =3V
C
+
VOUT As VOUT goes from VDD to VDD /2, the
average voltage VDS is (3/4) VDD.
-
S
Since ID = IDS( 1+lXVDS) The average
current is IDS( 1+lX(3/4)VDD) .
-
Thus the average effective resistance is the ratio:
(3/4) VDD / IDS( 1+lX(3/4)VDD) = RDN
ID
VGS = VDD
IDS
slope = 1/RDN
VGS = 0
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VDD/2
VDD
Using a resistance of this value we get
discharge time estimate which is less
than 4% different from the correct
answer obtained by direct integration
VDS
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4
MOS I-V Characteristics in more detail
For simple digital circuit calculations the MOS transistor will be
essentially off (VGS < VT ) or fully turned on (VGS = VDD ), the power
supply voltage).
But if VGS = VDD the value of IDS depends on VGS, so we need
some more theory. In particular we want to:
1) Describe dependence of IDS on VGS and geometry
2) Describe the “break point” in VDS above which ID saturates.
ID
S
VGS
+

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G
ID = IDS X (1+ l VDS)
VGS = VDD
IDS
D
iD
+
- VDS
off
EE 42 fall 2004 lecture 27
VDS
5
A little more MOS “Theory”
We have two regions: the resistive region at smaller VDS and the
saturation region at higher VDS .
In the resistive region we start out like a simple resistor between
source and drain (whose value depends on gate voltage) and gradually
the curve “bends over” as we approach saturation
In the saturation we have a small gradual increase of I with VDS
We call the boundary between the regions VDSat.
ID
Now we wish to describe the
dependence of the current on VGS
S
VGS
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+

VGS
G
D
iD
+
- VDS
VDS
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VDSat
Below threshold
VGS < Vt
-
+
gate
drain
source
oxide insulator
n
n
P
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Below threshold, there are
no electrons under the gate
oxide, and the holes in the
substrate are blocked from
carrying current by reverse
biased diode junctions
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NMOS in the linear (Triode) region
VGS > Vt
-
+
gate
drain
source
oxide insulator
n
n
P
If the gate voltage is above
threshold, but the source to
drain voltage is small, the
charge under the gate is
uniform, and carries current
much like a resistor
The electrons move under the influence of the
Electric field at a velocity: ν=μE where E=volts/distance
And they must travel a distance L to cross the gate
Since the total charge is Q=CVgs, we will have a current
Id=μCgateVds (Vgs-Vth)/L2= μ(εox/dox)Vds (Vgs-Vth)W/L
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NMOS with increasing Vds
VGS > Vt
-
+
gate
drain
source
oxide insulator
n
n
P
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As the voltage from the
source to the drain is
increased, the current
increases, but not by as
much because the charge is
attracted out from under the
oxide, beginning to pinch off
the channel
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Saturation
• As the Source-Drain voltage is increased, there will be a
significant change in the charge at different distances
along the gate
• When the voltage across the device at the drain end
goes below threshold, the current is pinched off.
• If there is no current out the drain end, however, the
current due to the carriers which are available from the
source cause the voltage to be closer to that of the
source.
• These two effects cause a small region to form near the
drain which limits the current. This is called saturation
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NMOS in saturation
VGS > Vt
-
+
gate
drain
source
oxide insulator
n
n
P
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When the voltage from the
source to the drain gets
high enough, the channel
gets “pinched” In the pinch
region, the carriers move
very fast, but the current is
determined by the triangular
region, which does not
change much as the drain
voltage is changed, so the
current saturates
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11
Submicron MOS
• In the last few years, transistors have become
so small that some of these approximations are
breaking down:
• As the transistors get short, the difference
between the triode region and saturation has
become blurred, with no clear saturation
• Because gate oxides are so thin, some current
goes through the gate in a process called
tunneling
• Sub-Threshold currents are increasing, causing
the transistors to conduct a small amount even
when they are supposed to be off.
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MOS “Theory”, con’t
In the saturation region (VDS >VDSat ) all the curves are described by
ID = IDS X (1+ l VDS) but IDS is a function of VGS.
In modern devices the saturation current is proportional to (VGS-VT).
The simple field effect gives us the idea for this proportionality: As
we increase VGS there is some “threshold”, VT. above which
electrons accumulate on the surface. The current is of course
proportional to the number of these electrons, so it is proportional to
(VGS -VT).
In figure below VT = 1V. Note that the current is proportional to (VGS
-VT), for example the current at VGS =3V is double that at VGS =2V.
The intercepts with the current axis
(IDS) depends not only on the gate
voltage, but also on device geometry.
We will next discuss how IDS depends
on device geometry.
ID
VDS
1/l
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VGS
VDSat
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NMOS TRANSISTOR STRUCTURE
• NMOS = N-channel
Metal Oxide Silicon
Transistor
“Metal” gate (Al or
Si)
Contact to
Drain
Contact to
Source
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gate length
• The gate length, L, is the distance the electrons
have to travel. It is generally set at the minimum
value (eg .18 micron) for nearly all logic
transistors
• As the gate length gets shorter, the gate
capacitance gets smaller
• As the gate length gets shorter, the current drive
of the transistor also gets larger.
• However, leakage current also increases
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Gate width
•The gate width, W, is determined by the
circuit designer. One uses a wider gate to
get more current (and thus charge a
capacitor faster). For example doubling W
is the same as putting two equal-sized
transistors in parallel, and thus doubles the
current at any given voltage.
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NMOS TRANSISTOR CAPACITANCE
“Metal” gate (Al or
Si)
Contact to
Drain
Contact to
Source
dOX = oxide thickness
• The gate is insulated from the rest of the transistors, but it has a
substantial capacitance to the source as it builds up charge in the channel
• The capacitance is proportional to W and L (for logic, mostly L is fixed, so
in effect C is proportional to the gate width W that the designer chooses. It
is inversely proportional to dOX .
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MOS TRANSISTOR – TOP VIEW
Drain
contact
W
Gate (over oxide)
Source
contact
Thin
oxide
What are device dimensions? Gate Length = L
and is fixed for any technology. (Such as the
.09-0.18 mm technology in manufacturing
today).
Gate Width = W and is selected by the
L
circuit designer for the current required.
The device current is proportional to W as well
as (VGS -VT), so we express IDS as a constant
times ( IDS' ) times W times (VGS -VT). ( Thus
the units of the constant IDS' are mA/V-mm.) We
multiply IDS' by the gate width W and by (VGS VT). to get the value of IDS in mA.
ID = IDS X (1+ l VDS)
and
IDS = W X IDS' (VGS -VT).
Example: a “1/4mm device” with IDS' = 75 mA/V-mm , W = 5mm, l= 0.02 V1, V = 0.5V and in a circuit with V
T
DD = 2.5V. If the device were 5mm wide
and the gate were at VDD then IDS = 5 X 75 (2.5 -0.5) = 750mA.
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MOS TRANSISTOR – TOP VIEW
Drain
contact
W
Gate (over oxide)
Source
contact
L
Gate Capacitance: The dimensions of
the capacitor are area = W X L and
thickness = dOX . A typical value, say for
“1/4 mm” technology, is 5nm.
The capacitance formula from physics is C=εA/d
= W X L X eOX / dOX.
The dielectric constant for oxide, eOX, is 3.9 eO =
3.45X10-13 f/cm.
If dOX = 5nm then eOX / dOX =7fF/mm2 of capacitor
so C=7W X L (fF) with W and L in mm.
Example: The same “1/4mm device” device with, W = 5mm. The gate
capacitance is 5 X 0.25 X 7 fF = 8.6 fF.
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Controlled Switch Model of Inverter (Lect. 18)
VDD = 3V
VIN =3V
This is what
we use the
NMOS for
+
RN
- SS = 0V
V
VOUT
-
If there is a capacitance at
the output node (there
always is) then VOUT
responds to a change in VIN
with our usual exponential
form.
VOUT
VDD = 3V
VIN =0V
Output when
VIN jumps from
3V to 0V
RP
+
VOUT
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- SS = 0V
V
-
3
0
EE 42 fall 2004 lecture 27
VIN jumps from
0V to 3V
t
20
Purpose of the NMOS Switch
The MOS transistor discharges C (some load).
G
D
+
VIN- =3V
C
S
-
ID
+
VOUT The NMOS switch is great for
discharging a node to ground. When
- VIN goes high (VDD ) then VOUT goes
from VDD to ground. When it reaches
VDD /2 we call that time the stage delay.
VGS = VDD
But we also need a switch to charge a
node, i.e. bring it from ground up toward
VDD . That’s where we need another
type of transistor, the PMOS. It makes
the ideal switch to charge the node.
IDS
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VDD/2
VDD
VDS
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CIRCUIT SYMBOLS
D
G
D
G
S
NMOS circuit symbol
S
PMOS circuit symbol
A small circle is drawn at the gate
to remind us that the polarities are
reversed for PMOS.
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NMOS =device which carrier current using electrons but
on the surface of a p-type substrate (p-type substrate
means that no electrons are available)
N-MOS gate
source
drain
oxide insulator
n
In this device the gate controls
electron flow from source to drain.
(in the absence of gate voltage,
current is blocked)
n
P
VGS > Vt
-
+
gate
drain
source
oxide insulator
n
n
If we increase gate voltage
to a value greater than Vt
then a conducting channel
forms between source and
drain. (“Closed switch”)
P
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CMOS = Complementary MOS
(PMOS is a second Flavor)
source
N-MOS gate
drain
oxide insulator
n
n
P
In this device the gate controls
electron flow from source to drain.
It is made in p-type silicon.
The NEW FLAVOR! P-MOS
gate
In this device the gate controls hole
flow from source to drain.
It is made in n-type silicon. (In ntype silicon no positive charges
(“holes”) are normally around.)
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source
P-MOS
p
EE 42 fall 2004 lecture 27
drain
p
n-type Si
24
PMOS
gate
In this device the gate controls hole
flow from source to drain.
source
P-MOS
p
The body is n-type silicon.
drain
p
n-type Si
|VGS |>|Vt |
+
gate
drain
What if we apply a big negative
voltage on the gate?
If |VGS |>|Vt | (both negative)
p
p
source
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n-type Si
then we induce a + charge on
the surface (holes)
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NMOS and PMOS Compared
NMOS
“Body”
– p-type
Source – n-type
Drain
– n-type
VGS
– positive
VT
– positive
VDS
– positive
ID
– positive (into drain)
G
S
D
ID
n
n
p
ID
B
ID
VGS=3V
1 mA
(for IDS =
1mA)
VGS= 3V
1 mA
(for IDS =
-1mA)
VGS=0
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PMOS
“Body”
– n-type
Source – p-type
Drain
– p-type
VGS
– negative
VT
– negative
VDS
– negative
ID
– negative (into drain)
G
S
D
ID
p
p
n
B
VGS=0
EE
V 42 fall 2004 lecture 27
1
2
3
4
DS
1
2
3
4
VDS
26
PMOS Transistor Switch Model
Operation compared to NMOS: It is complementary.
VDD
S
G
VDD
S
S
G
G
VDD
VG =0
VG = VDD
V=0
D
Switch OPEN
D
Switch CLOSED
D
For PMOS for the normal circuit connection is to connect
S to VDD (The function of the device is a “pull up”)
Switch is closed: Drain (D) is connected to Source (S) when VG =0
Switch is open :
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Drain (D) is disconnected from Source (S) when VG = VDD
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PMOS Model Refinement
PMOS transistor has an equivalent resistance RDP when closed
There is also a gate capacitance CGS, just as in NMOS
S
CG
S
G
P Ch
S
G
D
RDP
The circuit symbol
D
The Switch model
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CMOS
Challenge: build both NMOS and PMOS on a single silicon chip
NMOS needs a p-type substrate
PMOS needs an n-type substrate
Requires extra process steps
D
G
S
G
D
S
oxide
p
p
n-well
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n
n
P-Si
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