Transcript Lecture #42: Transistors, digital • This week we will be reviewing the material learned during the course • Today: review – CMOS transistors – Digital.

Lecture #42: Transistors, digital
• This week we will be reviewing the
material learned during the course
• Today: review
– CMOS transistors
– Digital logic
12/10/2004
EE 42 fall 2004 lecture 42
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Review Session
• When: Thursday, Dec. 16th; 3-6pm
• Where: Evans 0009
• Format: Open, bring questions
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EE 42 fall 2004 lecture 42
2
Final Exam
Date/Time:
• SATURDAY, DECEMBER 18, 2004
• 5-8PM
Location: 150 GSPP
(Goldman School of Public Policy)
Format:
• Closed book
• One page, (two sides) of notes
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MOS transistor
Below threshold
VGS < Vt
-
+
gate
drain
source
oxide insulator
n
n
P
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Below threshold, there are
no electrons under the gate
oxide, and the holes in the
substrate are blocked from
carrying current by reverse
biased diode junctions
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NMOS in the linear (Triode) region
VGS > Vt
-
+
gate
drain
source
oxide insulator
n
n
P
If the gate voltage is above
threshold, but the source to
drain voltage is small, the
charge under the gate is
uniform, and carries current
much like a resistor
The electrons move under the influence of the
Electric field at a velocity: ν=μE where E=volts/distance
And they must travel a distance L to cross the gate
Since the total charge is Q=CVgs, we will have a current
Id=μCgateVds (Vgs-Vth)/L2= μ(εox/dox)Vds (Vgs-Vth)W/L
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NMOS with increasing Vds
VGS > Vt
-
+
gate
drain
source
oxide insulator
n
n
P
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As the voltage from the
source to the drain is
increased, the current
increases, but not by as
much because the charge is
attracted out from under the
oxide, beginning to pinch off
the channel
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Saturation
• As the Source-Drain voltage is increased, there will be a
significant change in the charge at different distances
along the gate
• When the voltage across the device at the drain end
goes below threshold, the current is pinched off.
• If there is no current out the drain end, however, the
current due to the carriers which are available from the
source cause the voltage to be closer to that of the
source.
• These two effects cause a small region to form near the
drain which limits the current. This is called saturation
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A little more MOS “Theory”
We have two regions: the resistive region at smaller VDS and the
saturation region at higher VDS .
In the resistive region we start out like a simple resistor between
source and drain (whose value depends on gate voltage) and gradually
the curve “bends over” as we approach saturation
In the saturation we have a small gradual increase of I with VDS
ID
S
VGS
+

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VGS
G
D
iD
+
- VDS
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VDS
8
Basic CMOS Inverter
Inverter
CMOS
Inverter
IN
VDD
OUT
IN
VDD
p-ch
OUT
n-ch
Al “wires”
IN
VDD
PMOS Gate
Example layout of
CMOS Inverter
N-WELL
OUT
NMOS Gate
GROUND
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Al “wires”
IN
VDD
PMOS Gate
N-WELL
OUT
NMOS Gate
GROUND
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NMOS TransistorV
DS
- +
VGS
drain
gate
- +
source
ID
IG
metal
oxide insulator
metal
n-type
metal
n-type
p-type
metal
G
IG
ID
S
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-
VDS +
D
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NMOS I-V Characteristic
G
IG
ID
S
-
VDS +
D
• Since the transistor is a 3-terminal device, there
is no single I-V characteristic.
• Note that because of the insulator, IG = 0 A.
• We typically define the MOS I-V characteristic as
ID vs. VDS
for a fixed VGS.
• The I-V characteristic changes as VGS changes.
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NMOS I-V Curves
ID triode mode
saturation mode
VGS = 3 V
VDS = VGS - VTH(n)
VGS = 2 V
VGS = 1 V
cutoff mode (when VGS < VTH(N))
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VDS
13
Saturation in a MOS transistor
• At low Source to drain voltages, a MOS transistor looks
like a resistor which is “turned on” by the gate voltage
• If a more voltage is applied to the drain to pull more
current through, the amount of current which flows stops
increasing→ an effect called pinch-off.
• Think of water being sucked through a flexible wall tube.
Dropping the pressure at the end in order to try to get
more water to come through just collapses the tube.
• The current flow then just depends on the flow at the
input: VGS
• This is often the desired operating range for a MOS
transistor (in a linear circuit), as it gives a current source
at the drain as a function of the voltage from the gate to
the source.
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VDD
CMOS DIGITAL LOGIC
A
NAND gate
C= A B
A
B
AB
0
0
0
1
0
0
1
1
1
1
0
1
0
1
1
0
C
B
Making a NAND gate: (NMOS pulls “down”, PMOS “up”)
NMOS portion: both inputs need to be high for output to
be low  series
PMOS portion: either input can be low for output to be
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high
 parallel
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Logic Gates
These are circuits that accomplish a given logic function such as “OR”. We will
shortly see how such circuits are constructed. Each of the basic logic gates has a
unique symbol, and there are several additional logic gates that are regarded as
important enough to have their own symbol. The set is: AND, OR, NOT, NAND,
NOR, and EXCLUSIVE OR.
A
A
AND
C=A·B
B
B
A
B
A
C=A+B B
OR
A
A
NOT
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A
B
NAND
C = A B
NOR
C = AB
C  AB
EXCLUSIVE OR
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Transistor Inverter Example
It may be simpler to just think of PMOS and NMOS transistors instead
of a general 3 terminal pull-up or pull-down devices or networks.
VDD
VDD
Pull-Up
Network
VIN-U
IOUT
Pull-Down
Network
VIN-D
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VIN-U
Output
IOUT
VOUT
VIN-D
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p-type MOS
Transistor
(PMOS)
Output
n-type MOS
Transistor
(NMOS)
VOUT
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Complementary Networks
• If inputs A and B are connected to parallel NMOS, A
and B must be connected to series PMOS.
• The reverse is also true.
• Determining the logic function from CMOS circuit is
not hard:
– Look at the NMOS half. It will tell you when the output is
logic zero.
– Parallel transistors: “like or”
– Series transistors: “like and”
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Some Useful Theorems
1)
A B  BA
2)
AB  BA
Defined from
truth tables
Communicative
3) A  B  C  C  B  A
Associative
4) A  B  C  C  B  A
5) A  A  0
6) A  A  1
7) A  B  A  C  A  (B  C)
Distributive
8) A  B  A  B
9) A  B  A  B
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Each of these can be
proved by writing out
truth tables
} de Morgan’s Laws
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Evaluation of Logical Expressions with “Truth Tables”
The Truth Table completely describes a logic expression
In fact, we will use the Truth Table as the fundamental meaning
of a logic expression.
Two logic expressions are equal if their truth tables are the
same
A truth table can be turned into a sum-of-products by writing
each row which results in a “1” output as an “and” (the
product), and then ORing them together (the sum)
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Going from a Boolean expression to gates
NAND GATE SYNTHESIS. Using De Morgan’s theorem we can turn any
Boolean expression into NAND gates.
Simply expand the Boolean expression into a SUM-OF-PRODUCTS expression:
Y = ABC+DEF
Then rewrite it by “inverting” with De Morgan:
Y  (ABC)  (DEF) Clearly this expression is realized with three NAND
gates: one three-input NAND for (ABC) , one for
(DEF) , and one two-input gate to combine them:
A
B
C
The NAND realization, while based on
Y
DeMorgan’s theorem, is in fact much
D
E
simpler: just look at the sum of products
F
expression and use one NAND for each term
and one to combine the terms.
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Synthesis
Designing the combinatorial logic circuit, con’t
Method 3: NAND GATE SYNTHESIS (CONTINUED).
Two Examples of SUM-OF-PRODUCTS expressions:
X  AB  AB (X-OR function)
Y  ABC  ABC
A
B C
A
X
Y
B
(No connection)
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We could make the drawings simpler
by just using a circle for the NOT
function rather than showing a oneinput NAND gate
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CMOS NAND GATE
NMOS switches in series from output to ground; PMOS
switches in parallel from output to the supply (Here we
left out the A-A and B-B connection for clarity)
NAND: If either output is low then
one of the bottom (pull down)
series switches is open and one
of the upper (pull up) switches
are closed.
VDD
vA
vB
vOUT
vB
vA
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Thus the output is pulled high.
Behaves like 2 Rn’s in series
when both A and B are high
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NAND Gate Pull-Up Model*
VDD
vA
Output is loaded by the gate capacitance of
the next stage: C= CGn+CGp
Rp
vB
v OUT
vB
vA
Rp

C  CGn  CGp
C
One or both switches closed
(worse case: one switch)
t = RC = RpC  R p (CGn  CGp )
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NAND Gates
with more inputs
VDD
VDD
A
A
F
F
B
B
C
2-input NAND
3-input NAND
Each input loads with CGN +CGP
Output drives with 2RDN or RDP
Each input loads with CGN +CGP
Output drives with 3RDN or RDP
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CMOS NOR GATE
NOR function (two inputs)
A
B
A +B
C=A +B
0
0
0
1
0
1
1
0
1
0
1
0
1
1
1
0
VDD
A
B
C
Output is high only if both inputs are low 
A
B
PMOS switches (between the supply and
the output) in series
Output is low if either input is high 
NMOS switches (between ground and the
output) in parallel
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CMOS NOR GATE
“Complementary” configuration to the NAND gate
NOR
VDD
NAND
vA
VDD
vA
vOUT
v OUT
vB
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vB
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Definition of Fanout
Fanout = number of gates that are connected to the driver
1
2
n
Fanout leads to increased capacitive load (and higher delay)
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Clocked logic
• If we put two latches into every feedback path,
and make sure both latches are never open at
the same time, we can insure predicable results.
A
B
C
Outputs

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
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Edge trigger
• If we use an edge trigger, then a single phase clock can
be used. An edge triggered flip flop will only change at a
rising or falling edge of the clock, so that the new state
will not feedback to its own value
A
B
C
Outputs
 edge trigger 
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Sequential logic
• The timing rules for sequential logic can be
summarized:
• Only one transition of the latches are allowed
per clock cycle, the change from one clock is not
allowed to circulate back through the logic to
effect itself.
• The clock speed will be limited by the slowest
path
• The fastest path must not be allowed to change
the state before changes have been latched out
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