Transcript Semiconductor Memory Design Organization of Memory Systems Driven only from outside Data flow in and out Memories may simultaneously select 4, 8, 16 …columns. A cell.

Semiconductor Memory
Design
Organization of Memory Systems
Driven only from outside
Data flow in and out
Memories may simultaneously
select 4, 8, 16 …columns.
A cell is accessed for reading by selecting its row and column.
Overall Architecture of Memory
Design
n=m=8
216=25,536 bits=
2Kb
RAM
• Read-write random access memories
(RAM)
– Store data in active circuits; information is
lost if the power supply is interrupted
• Common Types
– Static RAM (SRAM)
– Dynamic RAM (DRAM)
SRAM
• SRAM
– Store value in flip-flop circuits as long as
power is on
– High speed memories with clock cycles in
the range of 5 to 50 ns
DRAM
• DRAM
– Store values on capacitors
– Prone to noise and leakage problems
– Slower than SRAM, clocking at 50 ns to
200 ns.
– More dense than SRAM
RAM Timing Parameters
Write signal is active low
Tcycle: minimum time needed
in order to complete successive
read and write operation
tAC(read access time):
presentation of address
Until data is out
tAC =(0.5 to 0.8)Tcycle
Organization of Memory Systems
AND and NOR Decoders
Take an n-bit address.
Produce 2n outputs,
One of which is activated.
Problem:
n=6 implies
1. 64 NAND6
2. 64 inverters
It is difficult to implement
NAND6 in standard
CMOS
Predecoder Configurations
Use a 2 stage
design to implement
NAND6
Use logical effort
to determine
the best design
Structure of Two-Level Decoder
Need 12
precoders
since n=6
Each precoder
Will drive
24 final decoders
Wire 1: from A0, A1
Wire 2: from A2, A3
Wire 3: from A4, A5
Static RAM Cell Design
• Static Memory Operation
Basic SRAM and VTC
A wordline is used to select the cell
Bitlines are used to perform read and write operations on the cell
Cross Coupled Configuration
The cell can only flip its internal state when one of its internal cross VS.
During a read op, we must not disturb its current state.
During a write op, we must force the internal voltage to swing past VS to
change a state.
6T SRAM Cell
Can be replaced by
undoped polysilicon
to minimize area.
Use high threshold transistors to reduce leakage current.
Wordline and Double Bitline
Configuration
One wordline is enabled.
The decoder must drive: (2 gate cap + wire cap) x # of cells in a row
Design of Transistor Size for Read
Operation
Assume:
q=0 and qb=1
Initially: b=VDD, bb=VDD
Cbit is discharged through M1.
b begins to drop.
bb remains high.
Vbb and Vb is added to a
sense amplifier and stored on
a data buffer.
Upon completion of the read,
wl returns to 0 Cbig precharged
To VDD.
Bitline capacitance
Bitline capacitance: (S/D cap+ wire cap+S/D contact cap) X # of cells in a
column
Sizing of M3 and M1
Icell could charge the gate
capacitance of M2, thus
lowering qb.
Solution: Adjust the sizing of M3
and M1 to minimize changes in q.
W3/W1 can be determined.
Discharge time is controlled by
sizing of M3 and M1
Icell should be large enough to
Discharge bitline capacitance within
20% to 30% of the cycle time.
Icell=Cbit (dV/dT)
Write Operation
Transistor Sizing
VQB=0.4=VTN
SRAM Cell Layout
Optional materials
Column Pull-Up Configurations
Address Transition Detection
Circuit
Column Decoding and
Multiplexing
Column Selection
4-bit Column Address
Write Driver Circuit
Basic Read Circuitry
Differential Voltage Sense
Amplifier
Detecting “0” and “1”
Latch-based Sense Amplifier
Replica Circuit for Sense
Amplifier Clock Enable
Replica Cell Design
Basic Memory Architecture
Divided Wordline Strategy to
Reduce Power and Delay
Bitline Partition to Reduce Delay
Peripheral Circuits
•
•
•
•
Decoders
Sense Amplifiers
Column Precharge
Data Buffers