Transcript Design And Analysis Of A Novel 8T SRAM Cell

Design and Analysis of A Novel 8T SRAM Cell
Department of Microelectronic Engineering
&
Centre for Efficiency Oriented Languages
University College Cork, Ireland
&
Synopsys, Ireland
Jiaoyan Chen, Dilip Vasudevan, Emanuel Popovici,
Michel Schellekens, Peter Gillen
Email: [email protected]
December 14, 2010
Contents
 Motivation
 Architectures of 6T SRAM, 9T SRAM
and our 8T SRAM
 Adiabatic and Non-Adiabatic Operations
 SNM Comparison
 Dynamic Power
 Static Power
 Conclusion
Motivation
SOC Consumer Stationary Power Consumption (2008)
Roadmap –Cell Area Trend(ITRS 2008)
Consumer Portable Power Consumption Trend
(ITRS 2008 update)
SRAM consumes a lot of power and area
in chips.
Our aim is to built an efficient SRAM.
Conventional 6T SRAM
Technology:
90nm,65nm,45nm, 28nm…
Stability:
Static Noise Margin
(SNM) is getting Down.
Leakage Power:
a) Subthreshold leakage current
b) Gate oxide leakage current
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9T SRAM
Features:
a) 2 sub-circuits:
Upper : Writing
Lower: Reading
b) Minimal Sizing for the
upper part
c) SNM is much better
d) Lower leakage Power
(in super cut-off mode)
Z. Liu and V. Kursun, “Characterization of a novel nine-transistor sram cell,” IEEE
Trans. Very Large Scale Integr. Syst., vol. 16, no. 4, pp. 488–492, 2008
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Proposed 8T SRAM
Features:
a) 2 sub-circuits:
Upper :1. No GND Connection
2. Add One Sharing
transistor
Lower: Using PMOS
b) Half swing
BL and BL’ return to VDD/2
after writing or reading.
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Adiabatic Operations: Writing
PMOS P3 is used to meet the Adiabatic Principle:
No voltage difference before the transistor turns on
Adiabatic Operations: Reading
Simulation Waveforms
SNM Comparison (45nm)
Proposed 8T SRAM
Conventional 6T SRAM
Dynamic Power Comparison (1)
8*8
Array
1 Bit
Cell
Dynamic Power
Comparison (2)
62%
67%
Leakage Power Analysis
Temperature Variation
>90%
Process Variation (65nm) – TOX, VTH, U0
>90%
Process Variation (45nm) – TOX, VTH, U0
90%
Conclusion

Summary




Efficient 8T SRAM architecture
Improved SNM compared with 6T SRAM
Very Low Dynamic and Leakage power
Future work
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
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Use 36nm, 28nm…Check performance particularly for
leakeage
Further Enhance the Stability
Fabricate and validate the proposed architecture
Thank You
Questions?