Transcript BWRC retreat presentation

EE141 Project: 32x32 SRAM
Abhinav Gupta, Glen Wong
Optimization goals:
• Balance between area and performance
•Minimize area without sacrificing
performance
SRAM Cell Design
•6-T SRAM Cell
•Modified provided SRAM
cell to decrease area from
38.08μm2 to 31.68μm2.
•Inverter PMOS: 0.36μm
•Inverter NMOS: 1.08μm
•Pass Transistor: 0.54μm
Read and Write Noise Margins
Read Noise Margin Analysis
•Read Voltage Rise: 284mV
Write Noise Margin Analysis
•Write Cell Voltage: 181mV
Decoder Design
•Each input to the
Decoder was buffered
via inverters due to
branching.
•The split SRAM allows
for reduced Cfixed.
•The decreased size of
SRAM cell enables
lower load capacitance.
•Calculated Delay:
624.65ps
Decoder Implementation
•Layout of
final Decode
Stage on the
left consists of
3 inputs and 1
output.
•Simulated
delay of full
decoder:
547.51ps
Adder Design
A0
B0
0.72μm
0.72μm
C0
B1
A1
Mirror
Adder
C1
B2
A2
C2
Mirror
Adder
1.44μm
0.36μm
A3
C3
A4
1.44μm
0.72μm
S4BAR
0.72μm
0.36μm
0.72μm
0.36μm
0.72μm
0.36μm
S1
S0 0.36μm
0.72μm
S0BAR
S4
S2BAR
0.36μm
0.72μm
S1BAR
0.36μm
0.72μm
S3 0.36μm
S2
0.72μm
S3BAR
•Ripple-Carry Adder Chain
•Produces both Sum and its complement values
•Critical Path consists of initial carry generation to evaluation of MSB sum value
•Calculated Delay: 690.5ps
5fF
Adder Implementation
•Layout of Full Adder consists of 16
inputs and 10 outputs and is directly
connected to the pre-decode stage.
•Simulated delay of full decoder:
886.94ps
SRAM Array Design
Final Decoder
Final Decoder
16X32 SRAM
16X32 SRAM
Final Decoder
Adder
Final Decoder
Pre-Decoder
•Split SRAM Array to save wire capacitance between predecode and final-decode stages.
•Reduced SRAM Cell Size without decreasing transistor sizes
•Minimizing area of cell, and decode stage without affecting
delay/performance.
SRAM Array Layout
•Pre-Charge Devices only one side of SRAM (other side internally connected).
•Output Buffers only on one side of SRAM as well.
•Total Simulated Delay: 1.539ns
•Overall Area: 49,607μm2.