Cryo and AFE IIt Update MICE Collaboration Meeting October 22, 2005 RAL A. Bross.

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Transcript Cryo and AFE IIt Update MICE Collaboration Meeting October 22, 2005 RAL A. Bross.

Cryo and AFE IIt Update
MICE Collaboration Meeting
October 22, 2005
RAL
A. Bross
Cryo Update I
 The cryo-system for the VLPCs has been operated extremely
reliably and stably from May through the end of the KEK TB
 However, it was felt that the thermal-link design could be
made more robust

A bolted concept has now been detailed and will be used in all
subsequent systems
 The drawing package has been “marked-up” for update
 The drawing package is currently in the Fermilab drafting
queue.
 There are a few outstanding issues that still need some
thought


Is the top plate stiff enough against atmospheric pressure?
Can the new thermal link design permit non-positive clamping of
the cassette so that a cassette could be removed from the
cryostat without having to break the cryo-vacuum
Cryo Update II
AFE IIt Update
 The AFE IIt prototypes (10) have
arrived and are under test
 The production run of Tript chips is
complete, and approximately 8200 die
have been packaged.
 Enough for about 500 boards
AFE IIt
AFE IIt test Status

The AFE IIt board test is making very good progress

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Next Steps

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
All power applied (AFEI power supply values)
1553 communications functional
JTAG programming chain working
RT1553 FPGA operating properly
PIC microcontroller operating properly using new C code (at least for those tests
we have performed so far)
HELPER FPGA operating properly for the functions we have checked so far
CLOCKGEN FPGA operating properly, clocks being generated, phase control from
the PC, through 1553 is working properly.
Program and read the FLASH memory
Use the FLASH to program the DFPGAs
Use the FLASH to program the AFPGAs
ADC for measuring bias and temp is working
Bias DACs, heater DACs are working
Test the slow communications to AFPGAs and DFPGAs
Apply power to TriP-t chips and ADCs
Run the TriP-t and ADCs through the ACQUIRE/DIGITIZE/READOUT cycle
Lots of FPGA programming to Do!
TriPt
We now have all the packaged TriPts that will be needed
Preliminary testing:



Linearity problem at small charge input has indeed been fixed
A pulse output, Ch 6
A-pulse, Ch 6
2400
1200
2250
1180
1160
2100
1140
A output [mV]
A output [mV]
1950
1800
1650
1500
1120
1100
1080
1060
1350
1040
1200
1020
1050
1000
980
900
0
20
40
60
80
100
Qin [fC]
120
140
160
180
200
0.0
2.0
4.0
6.0
8.0
10.0 12.0 14.0 16.0 18.0 20.0
Qin [fC]
TriPt II
Bandwidth performance looks good
Measuring risetime. G=0111, R1=130, R5=255, 110mA
1455
1420
1385
1350
Amp output (mV)

C10, Qin=10fC
55nS for better than
7bit accuracy
1315
C10, Qin=40fC
1280
C16
1245
C22
1210
7 bit ilne
1175
1140
1105
1070
1035
1000
0
10
20
30
40
50
60
70
80
t integration (nS)
90
100 110 120 130 140
TriPt III
Discriminator Performance as expected

Likely not an issue with MICE
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
Ch8
Ch9
Ch10
Ch11
Ch12
Ch13
Ch14
Ch15
Ch16
50
Ch17
Ch18
40
Ch19
Ch20
30
Ch21
Ch22
20
Ch23
Ch24
10
Ch25
Ch26
Ch27
Ch28
15 Ch29
Ch30
Ch31
Ch32
Turn on curves for all 32 ch
100
90
80
70
Efficency (%)

60
0
0
1
2
3
4
5
6
7
8
Qin (fC)
9
10
11
12
13
14
TriPt IV

TDC gain
9
TDC gain [mV/ns]
8

7
6
5
4
3
2
1
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Ch number
T pulse output vs injection time
1950
T pulse output [mV]
TDC Gain has large
spread
1750
1550
1350
1150
950
0
10
20
30
40
50
60
70
80
90
100
T inject before end of w indow [ns]
110
120
130
140
150
This was expected and
can be taken out
(calibration) off-line
TriPt V
Time-walk as expected.
TAC output as a function of Qin
T-pulse output [mV]

1850
1825
1800
1775
1750
1725
1700
1675
1650
1625
1600
1575
1550
Ch1
Ch11
Ch21
Ch31
10
20
30
40
50
Qin [fC]
60
70
80
Issues that will Need some Thought
 AFE IIt board temperature and bias calibration

Does MICE need a test stand (like D0 has) to do this operation?
 LED pulser data

Plan to dismount wavguides and mount a LED pulser or excite the
fibers with blue LEDs?
 New LVSB Board
 AVNET (timing) board incorporated into LVSB or possibly the
AFE IIt can be programmed to take over the functionality of
the AVNET board
 Rate

If we keep analog and timing information we are limited to:

1/(150 X 19 ns) @ 350 muons per msec of spill
– It is possible that clever (extreme) programming of the AFE IIt can push
this up a bit – 400-450 or so.

If we drop analog and timing and only use discriminators, we can
run at 7 MHz.