Transcript TriP-t & AFEII status Paul Rubinov AFE and CFT 8 photons VLPC 9o K (x512) 80 fC Central Fiber Tracker cylinder Discriminator output every 396 nsec for L1 Amplitude signal readout for.

TriP-t & AFEII
status
Paul Rubinov
AFE and CFT
8 photons
VLPC
9o K
(x512)
80 fC
Central Fiber Tracker cylinder
Discriminator output
every 396 nsec for L1
Amplitude signal
readout for L3 and
offline
DISCR
ADC
AFE
Overview
Ancient history
build/test TriP for 132ns running
STOP
AFE1 problems
TriP works very well at 396ns and
adding time info can help CFT
a lot.
Build AFEII
prototype
Summer 04
milestone
Build TriP-T
Aug 04
Build AFEII (with time Info)
by end of 2005
AFEII proto current status
Schematic design is 99% complete. …an internal review has been
completed. The review committee made a number of suggestions (minor)
and these are being implemented.
Layout of the board is about 80% complete…
However, this is going very slowly. Still 3 weeks work left.
This puts the work about 3-6 weeks behind schedule. Has
impact on D0. Test of AFE II prototypes with beam this
August is now NOT likely.
Specifications for the new microcontroller code requirements are 75%
complete…
Design of the FPGA is 75% complete…
TriP


The existing TriP ASIC (7000 die on hand)
Lots of testing over about 18 months- described in
Fermi TM 2226, 2227 and 2228
TriP-t: the new idea


About 1% additional components:
7bits t-info offline: 120ns full scale=> 2ns time
resolution in Z
=> ~35cm
TriP-t current status
 The chip designers are chip designing.
 End date is given as Aug ’04
 The new chip is the “critical path” item for the
project

Assuming D0 makes decision to use Tript
 Some prep work going on now


We will need new packaging
We had some concerns about features
used on the new chip, but where not used on the old
(current!) TriP chip.
TriP-t prep work

Bench testing

New package