Transcript AFE II - International Muon Ionization Cooling Experiment
AFE II Status
Analog Front-End (AFE) Board
Approximately 200 AFE boards are needed to readout CFT (&CPS/FPS)
512 channel (2/cassette) Analog output via SVX IIe
Discriminator output every 396 ns for L1 trigger MultiChip module (MCM)
SIFT chip
– Analog buffer to SVX – Discriminator output
SVX IIe
AFE II
A Tremendous Effort has already gone into AFE II PPD EE Department John Anderson Jim Hoff Abder Mekkaoui Paul Rubinov D0 Alan Bross Juan Estrada Carlos Garcia Peter Hasiakos Bruce Hoeneisen Marvin Johnson Mike Utes
AFE II
AFE II
Full New set of boards No SIFT No SVX – Much simpler architecture Will use instead
Trigger Pipeline Chip: TriP (or Tript - more in a bit)
– Discriminators and analog pipeline – TriP chip submission was very successful – meets spec.
Commercial Flash ADCs + FPGA for analog information Integrates completely with existing system
Will Have
No Front-end saturation problem
– Reset once per crossing – Also allows for data taking in abort gap (cannot do presently with AFE I) • VERY
useful for Calibration studies Improved Ped dispersion and stability
– Lower and tighter threshold setting capability • Channel by Channel - analog
Improved reliability Improved readout flexibility
– Decreased deadtime – Multi-buffering possible • CFT Readout may dominate L1 readout rate without multi-buffering
Added Functionality with new submission of TriP Chip - Tript
– z information from timing (
2 ns rms)
TriP
The existing TriP ASIC (7000 die on hand) Lots of testing done over last 2 years
AFE II –TriP Performance
Measurements on TriP very promising
Noise at 1/5 pe rms Threshold setting at 1.5 pe reliably Very high quality Analog Data Plot at right was obtained after 1 day of work on a TriP modified AFE board
To get this good, a plot with the AFE took about 1 month of dedicated work by the same people!
BLACK – DATA
RED – FIT All Discriminators Firing!
AFE II – TriP Discriminator Performance
Upper plot
Red – all data Blue same data with threshold and discriminator fires Black – fit Lower plot
Ratio of analog data with and without discriminator fires (threshold set)
47% occupancy
TriP-t: the new idea
About 1% additional components:(time to amplitude converter) 7 bits t-info offline: 120ns full scale=> 2ns time => ~30cm resolution in Z
AFE II - TriPt
With a rather simple modification to the TriP design – time stamp for hits can be obtained Current TriP
Electronics resolution was determined to be
400 ps For 8 pe signal expect about 2 ns sigma
Z measurement –
30 cm Has impact on reco time and cluster splitting
In Z
mm
+15 min bias MC 40-60% reduction in reco time D0 Note 4497 Improvement in clustering algorithm utilizing z info also a possibility
400 ps intrinsic resolution
Bench testing
TriP-t prep work
New package
TriP-t current status
The chip designers are chip designing.
Ready for submission 23 Aug ’04 The new chip is the “critical path” item for the project Some prep work going on now
We will need new packaging We had some concerns about features used on the new chip, but not used on the old (current!) TriP chip, so we are retesting some things.
Full Project Plan Now Available
AFE II - Cost and Schedule
AFEII Prototype - current status
Schematic design is 100% complete. Internal review was held in early May.
Layout of the board is about 95% complete.
All parts are here.
Req’s for boards are in the system.
RFQs for stuffing are on the street.
Firmware about 75% complete.
AFE II – Cost and Schedule
Cost M&S:
Production cost M&S are based on quotes for parts and labor – contingency estimate is grounds up: Manpower
Estimates from AFE experience Schedule critical path is the Tript chip Completion for the 05 Shutdown is not likely Planning for adiabatic Installation
AFE I and AFEII mixed running Will need to test compatibility once AFE II prototypes are ready (9/04) Installation will have to be done at the crate level (16 boards) because of difference in power requirements for AFE I and AFE II Credibility of installation plan is dependent on prototype tests
How quickly they come up
Platform test and integration with trigger Software readiness Physical Installation can occur quickly (8 hour)
AFE II Milestones
AFE II Prototype under test Tript MOSIS submission D0 Internal Review
May be moved up to October AFE II production AFE II production complete 9/04 9/04 1/05 Director’s Review
May be moved up to Novemeber Tript production submission
3/05 Possibility for “non-shared” submission in 12/04 AFE II pre-Production
Attempt to move up to 11/05 Boards available for KEK Test?
2/05 7/05 9/05 12/05 First Board Ready for installation 2/06
Conclusions – Improvements with AFE II
AFE II will
Improve noise floor and pedestal stability which will allow for consistent and reliable threshold setting with no discriminator feed-through or discriminator threshold shift
Will increase physics trigger efficiency Potential for better hit efficiency and point resolution Maintain capability of Preshower Detectors No Front-End Saturation problem (reset once per crossing) Added functionality of the Tript (z information)
Large reduction in reco time Possible improvement in cluster finding
– Cluster splitting leading to additional improvement in track quality
Readout architecture much more flexible
Less deadtime Multiple buffers can be added to greatly increase L1 capability Board construction is simpler, more robust
No MultiChip modules (MCM) Mostly commercial parts/standard mounting techniques Repairs/rework MUCH easier than in AFEI AFEII will improve our capability to maintain high-quality and stable operation as the Tevatron Luminosity increases in RunII. This will allow D0 to maintain excellent tracking, trigger, and Preshower performance
DAQ System
We need to build a clone of the new test stand DAQ that is being put together at D0
New DAQ
Consists of (for 4 Board Readout)
VIPA crate (10U)
Bit3 controller 1553 controller VRB (VME readout bus) VRBc (VRB controller) Serial command link receiver card (SCLr) Sequencer crate
Sequencer controler (SEQc) + SCLr Sequencer 2 fibers for connection of the VTM 2 grey cables for connection to the AFEs (2AFEs/cable) AFE
4 (+2) Boards (minimum) Two backplanes for cyostat.
PC and custom cables Special trigger cards (2) (STDB) Hardware for downloads of firmware for AFE, SEQ, VRBc, and SEQc
New DAQ
Cost (k$)
VME SEQ 1 1 1553 1 Power supplies 2
AFE BPs 2 Bit3 controller 1 SEQc AFEIIs SCLr cards 2 4/each (X6) 2 Rack Cables, misc.
1 4
TOTAL:
$40-50K
New DAQ
We have started work on the DAQ. However there is a great deal of work to do to have a system ready for the KEK test There is also a VERY steep learning curve on becoming an expert on this system and at least one will be needed for the beam test.
So Far I have not been able to get additional Fermi people interested or, at least, committed to it (there is interest).