InGaAs MOSFET with self-aligned Source/Drain by MBE regrowth Uttam Singisetti*, Mark A.
Download ReportTranscript InGaAs MOSFET with self-aligned Source/Drain by MBE regrowth Uttam Singisetti*, Mark A.
InGaAs MOSFET with self-aligned Source/Drain by MBE regrowth Uttam Singisetti*, Mark A. Wistey, Greg J. Burek, Erdem Arkun, Ashish K. Baraskar, Brian J. Thibeault, C. J. Palmstrøm, A.C. Gossard, and M.J.W. Rodwell ECE and Materials Departments University of California, Santa Barbara, CA, USA Yanning Sun, Edward W. Kiewra, and D.K. Sadana IBM T J Watson Research Center, Yorktown Heights, NY, USA 2008 International Symposium on Compound Semiconductors Rust, Germany *[email protected] ISCS 2008 Outline • Motivation: III-V MOSFETs • Approach: Self-aligned source/drain by MBE regrowth • FET and Contacts Results • Conclusion ISCS 2008 Why III-V MOSFETs Silicon MOSFETs: • Scaling limit beyond sub-22 nm Lg • Non-feasibility of sub-0.5 nm equivalent oxide thickness (EOT) Alternative III-V channel materials III-V materials→ lower m*→ higher velocities (veff) Id / Wg = qnsveff Id / Qtransit = veff / Lg In0.53Ga0.47 As : m* 0.041 m, veff ~ vth 3.5 107 cm / s ISCS 2008 22 nm InGaAs MOSFET 4 source contact N+ source Al2O3 Lg gate dielectric 2 InGaAs InP metal gate drain contact InGaAs channel N+ drain InAlAs barrier Enegy(eV) L S/D InAlAs 0 -2 InP substrate Predicted drive current: ~5 mA/mm1,2 -4 -6 0 50 100 150 Y (Ang.) 200 250 Key Challenges • 1 nm EOT gate dielectric • 5 nm channel with back barrier • 15 W-mm source resistance • 5×1019 cm-3 source active doping2 1 2 Rodwell. IPRM 2008 Fischetti. IEDM 2007 ISCS 2008 InGaAs MOSFET with Source/Drain regrowth metal gate Process scalable to 22 nm InGaAs quantum well barrier substrate Source/Drain defined by metal gate MBE regrowth InGaAs quantum well barrier substrate Regrowth InGaAs, in situ Mo sidewall metal gate N+ source InGaAs quantum well N+ drain barrier contact Resistance: 0.5 W-mm2 (2.5 W-mm)* substrate gate dielectric sidewall metal gate source contact N+ source drain contact InGaAs quantum well barrier substrate N+ drain * Wistey, EMC 2008 ISCS 2008 Process flow Gate definition blanket metal Sidewall, Source/Drain sidewall r Ti/W gate oxide InGaAs channel InP subchannel barrier r r r well well well SI substrate (starting material) blanket gate deposition etch gate, etch dielectric etch upper channel sidewall formation S/D regrowth S/D contacts mesa isolate S/D ISCS 2008 Gate Definition: Challenges r r r well InP well barrier ion damage • Must scale to 22 nm • Dielectric cap surrounding the gate for source/drain regrowth • Metal & Dielectric etch must stop in 5 nm channel • Dry etch must not damage thin channel Process must leave surfaces ready for S/D regrowth ISCS 2008 Gate Stack: Multiple Layers & Selective Etches Key: stop etch before reaching dielectric, then gentle low-power etch to stop on dielectric FIB Cross-section resist SF6 / Ar etch 50 W Cl2 / O2 etch 15 W SiO2 W gate metal Damage free channel Cl2 / O2 etch 15 W Cr etch stop SF6 / Ar etch 15 W SiO2 Cr etch mask Cr dielectric KOH wet etch Al2O3 (r) InGaAs well W InP well barrier SI substrate Dry etch scheme Process scalable to sub-100 nm gate lengths ISCS 2008 Dielectric etch and sidewall formation r r 40 nm SiN sidewall dil KOH r InGaAs well InP well barrier Dielectric etch r InGaAs well InP well barrier Sidewall definition r r well InP well barrier InGaAs etch ISCS 2008 Surface cleaning before regrowth • Clean organics by 30 min UV Ozone • Ex-situ HCl:H2O clean HAADF-STEM* InGaAs regrowth Interface • In-situ 30 min H clean • c(4×2) reconstruction before regrowth InGaAs 2 nm • Defect free regrowth Epi-ready surface before regrowth, defect free regrowth on processed wafer * Wistey, EMC 2008 ISCS 2008 Height selective Etching* PR Mo r Planarize r r r well InP well barrier well InP well barrier InGaAs r Strip PR r r r well InP well barrier well InP well barrier ICP O ash 2 PR r r SF6/Ar Mo etch InGaAs wet etch PR well InP well barrier Dummy gate No regrowth * Burek, J.Cryst.Growth, submitted for publication ISCS 2008 MOSFET characterstics 100 100 Lg 10 microns, Wg 50 microns g Vg 0 V to 2 V in 0.25 V steps Drain current ( mA) Drain Current, uA 80 L =10mm, W =50mm 60 40 g V =2V 80 ds 60 40 Rs ~ 1 MW-mm! 20 20 0 0 0 0 0.5 1 Vds, Volts 1.5 0.5 2 • • Extremely low drive current: 2 mA/mm Extremely high Ron= 10-100 kW • Why is Rs so high? 1 V (Volts) 1.5 2 gs ISCS 2008 Source Resistance 1: Poly Growth on InP After regrowth Rough InGaAs regrowth SEM InGaAs regrowth on unprocessed thin InP* • • Spotty RHEED during regrowth: faceted growth InP desorbs P during hydrogen clean or regrowth: InP converts to highlystrained InAs* • From TLM measurement, Rsh= 310 W/□, rc=130 W-mm2 and Rs= 300 W-mm Sheet resistance doesn’t explain 1 MΩ-µm source resistance. * Wistey (in preparation) ISCS 2008 Source Resistance 2: Gap in Regrowth SEM InGaAs regrowth 1200 SEM g 1000 SiO2 800 W / Cr / SiO2 W No regrowth gate r 600 InGaAs InP d Electron depletion N+ regrowth InGaAs regrowth Gap ~ 200 nm Cr No regrowth I (mA) W / Cr / SiO2 gate L = 10 mm W=10 mm V =0.0 V Electron depletion barrier 400 200 0 0 2 4 V (V) 6 8 ds • No regrowth within 200 nm of gate because of shadowing by gate • Gap region is depleted of electrons • Breakdown at Vg=0V, ~ 8V, consistent with 400 nm gap and InGaAs breakdown field of 20V/mm* High source resistance because of electron depletion in the gap *http://www.ioffe.rssi.ru/SVA/NSM/Semicond/ ISCS 2008 Regrowth: Solutions smooth InGaAs regrowth on thin InGaP* High T migration enhanced Epitaxial (MEE) regrowth* No Gap gate regrowth interface *Wistey, EMC 2008 Wistey, ICMBE 2008 ISCS 2008 Conclusion • Scalable III-V MOSFET process with self-aligned source/drain with MBE regrowth • Gate proces and H clean leave a epi-ready 5 nm channel • Low drive current in initial devices because of break in regrowth • Improved regrowth techniques in next generation of devices This work was supported by Semiconductor Research Corporation under the Non-classical CMOS Research Program ISCS 2008