215th ECS Meeting, San Francisco, May 28, 2009 III-V/Ge Channel Engineering for Future CMOS Mark A.
Download ReportTranscript 215th ECS Meeting, San Francisco, May 28, 2009 III-V/Ge Channel Engineering for Future CMOS Mark A.
215th ECS Meeting, San Francisco, May 28, 2009 III-V/Ge Channel Engineering for Future CMOS Mark A. Wistey University of California, Santa Barbara Now at University of Notre Dame U. Singisetti, G. Burek, A. Baraskar, V. Jain, B. Thibault, A. Nelson, E. Arkun, C. Palmstrøm, J. Cagnon, S. Stemmer, A. Gossard, M. Rodwell University of California Santa Barbara [email protected], 805-893-3279 P. McIntyre, B. Shin, E. Kim Stanford University S. Bank University of Texas Austin Y.-J. Lee Intel Funding: SRC Outline: Channels for Future CMOS • FET scaling requirements... and failures • Motivation for Regrown MOSFETs • III-V Benefits and Challenges • Fabrication Process Flow • Depletion-mode MOSFETs • The Shape of Things to Come M. Wistey, Spring ECS 2009 2 Future CMOS Priorities High Performance High drive current Id / Wg for wiring Low gate delay CFET∆V/Id for local Low Parasitics Capacitance – already 1-2 fF/µm Resistance – already ~50% Rtot Leakage Currents – now 50% power Compatible with Existing CMOS High packing density –width & contacts small Growable on Si substrates M. Wistey, Spring ECS 2009 Graphics: Mark Rodwell Simple FET Scaling Goal double transistor bandwidth when used in any circuit → reduce 2:1 all capacitances and all transport delays → keep constant all resistances, voltages, currents reduce 2:1 all lengths, widths, thicknesses gm , Id held constant ✓ held constant ✓ (doubles mA/ m, mS/ m) ✓ reduced 2:1 edge capacitances reduced 2:1 ✓ substrate capacitances reduced 2:1 ✓ must reduce c 4:1 M. Wistey, Spring ECS 2009 Slide: Mark Rodwell 4 “External” Resistances are Critical Source Coverlap Lg Cfringing Drain Gate Dielectric, εr n+ tox Channel (p or NID) Rc Raccess xj n+ Cox Back Barrier Rsp & Rif & Rq Resistances constant ⇒ Resistivities must scale as 1/Lg2: • Contact resistance Rc • Access & spreading resistance • Interface resistance & source starvation • Sharvin resistance (quantized conductance): M. Wistey, Spring ECS 2009 5 Transconductance Scaling Challenges gm ~ (1/Cg-ch)vthWg ...Should stay constant (double mA/µm) But voltage divider exists: Gate Cox scales as 1/EOT ...EOT scales poorly Top Barrier or Oxide Csemi ~ εchan.LgW/d Channel Cdos = Bottom Barrier Thin channel tqw d tqw d E1 ...Smaller ...Smaller Thick channel ☹ ☹ ☹ CB E1 CB Wavefunction pushed away from gate Csemi scales poorly Similar problem with overlap & fringing capacitances. Solution: Increase vth using new material. M. Wistey, Spring ECS 2009 6 MOTIVATION FOR REGROWN FETs 7 Device Choice: Why not HEMTs? Wide recess→ okay DIBL, subthreshold slope, Cgd Wide contacts→ Rc okay even with poor contacts Injection thru barrier Long recesses, lightly doped = high Raccess HEMTs obscure scaling issues. M. Wistey, Spring ECS 2009 } Not scaled Low gate barrier = Limited carrier density Scalable III-V FET Design Classic III-V FET (details vary): Large Area Contacts Gap Gate Large Rc { Source { Large Raccess Drain Top Barrier or Oxide • Disadvantages of III-V’s { Channel Bottom Barrier InAlAs Barrier Low doping • Advantages of III-V’s III-V FET with Self-Aligned Regrowth: High Velocity Channel Small Raccess Small Rc High mobility access regions Self-aligned Gate High-k n+ Regrowth High doping: 1013 cm-2 avoids source exhaustion M. Wistey, Spring ECS 2009 High barrier Channel In(Ga)P Etch Stop InAlAs Barrier 2D injection avoids source starvation Low sheet resistance; dopants active as-grown 9 Big Picture: Salicide-like Process Analogy: Self-aligned silicide (salicide) process: Salicides Regrown Contacts Metal Gate Salicide High-k Channe l .... Advantages: Self-aligned No e- barrier CMOS-safe metals Metal Gate Source Contact n+ Regrowth High-k Channe l .... Barrier Take from Silicon: Unlike classic III-V devices: Avoid liftoff Dry etches Self-aligned processes Surface channels Do III-V fabrication in Si-like fashion. M. Wistey, Spring ECS 2009 Break from Silicon: No implantation Insufficient doping Surface damage Annealing is no panacea Encapsulate gate metals Arsenic capping Ship wafers for high-k Strain is cheap 10 III-V Benefits and Challenges 11 Channel Roughness Scattering •Challenge: Sixth power (!) scattering from interface roughness: µ ~ (1/Mscat)2 ~ 1/(∂E/∂W)2 ~ W6 (Gold SSC 1987) •Trend weaker in shallow or narrow wells (Li SST 2005) Fit: ~W-1.95 •Screening helps too •Does not seem to be a problem for 5nm InGaAs M. Wistey, Spring ECS 2009 12 Drive Current in the Ballistic & Degenerate Limits eot includes the electron wavefunction depth n m* / m0 1/2 3/ 2 mA Vgs Vth J K 84 m 1V where K 1 c dos,o / c ox m / m0 * 1/ 2 Inclusive of non-parabolic band effects, which increase cdos , InGaAs & InP have near-optimum mass for 0.4-1.0 nm EOT gate dielectrics Rodwell IPRM 2008 High Mobility in Narrow InGaAs Channels Hall Measurements No Shubnikov-de Haas Oscillations 4K InAlAs mobility: 346 Electrons occupy multiple channels But electrons aren’t in InAlAs...? • Unclear whether high mobility is in narrow channel • Unreasonable simulation difficulty. – Nonparabolic bands, degenerate statistics, bandgap renormalization, screening... • Need FET to remove uncertainty: eliminate doping altogether. M. Wistey, Spring ECS 2009 14 Regrowth Interface Resistances Interface resistances tested in separate blanket regrowths (no gates): In-situ Mo Contact c < 1 - m2 Source Contact 25 nm regrown InGaAs Rsh=70 /sq Metal Gate Drain Contact High-k n+ Regrowth InGaAs InP or InGaP etch stop InAlAs barrier InGaAs-InGaAs re-growth resistance < 1 - m2. InGaAs-InP re-growth resistance = 6 - m2 (on thick InP). FABRICATION PROCESS FLOW 16 Process Flow: Gate Deposition High-k first on pristine channel. Cr Tall gate stack. Litho. SiO2 Selective etches to channel. Metals Critical etch process: Stop on channel with no damage er NID InGaAs Channel InP/InGaP etch stop InAlAs barrier InP substrate M. Wistey, Spring ECS 2009 17 Gate Stack: Multiple Layers & Selective Etches Key: stop etch before reaching dielectric, then gentle low-power etch to stop on dielectric M. Wistey, Spring ECS 2009 Rodwell IPRM 2008 18 Process Flow: Sidewalls & Recess Etch SiNx or SiO2 sidewalls Encapsulate gate metals SiO2, SiNx Metals Controlled recess etch Slow facet planes Not needed for depletion-mode FETs er Channel InP/InGaP etch stop InAlAs barrier InP substrate M. Wistey, Spring ECS 2009 19 Surface Preparation Before Regrowth SiO2, SiNx O3 (g) UV-ozone (20 min) Metal er Channel HCl:H2O 1:10 etch (60 sec) H2O rinse, N2 dry SiO2, SiNx HCl+H2O (l) Metal er Channel Bake under ultrahigh vacuum Hydrogen cleaning 10-6 Torr, 30 min., 400°C (InP) or 420°C (InGaAs) Thermal deoxidation may work also. M. Wistey, Spring ECS 2009 SiO2, SiNx H2 + H (g) Metal er Channel 20 Clean Surface Before Regrowth InP etch stop Clean, undamaged surface after Al2O3 dielectric etch & InGaAs recess etch. M. Wistey, Spring ECS 2009 21 At Last: Regrowth & Metal Regrow n++ InGaAs Doping: n~3.6x1019 cm-3 (Si~8x1019 cm-3) V/III ratio=30 Tsub = 460°C SiO2, SiNx Mo n++ InGaA s Metals er Channel n++ InGaA s InP etch stop RHEED before growth InAlAs barrier Blanket metallization: Either in-situ Mo or ex-situ TiW Singisetti APL, submitted, or Crook APL 2007 M. Wistey, Spring ECS 2009 22 TEM of Regrowth: InGaAs on InGaAs HRTEM InGaAs n+ regrowth Interface HAADF-STEM` InGaAs n+ Interface 2 nm Regrowth on processed but unpatterned InGaAs. No extended defects. M. Wistey, Spring ECS 2009 23 Removing Excess Overgrowth 1. Spin on thick polymer Polymer 2. Mo & InGaAs Etch Approach #1: Remove it SiO2 Height-selective etch Wistey MBE 2008 & Burek JCG 2009 Metal Oxide Regrowt InGaAs h InGaP etch stop InAlAs barrier Polymer SiO2 Metal Oxide Regrowth InGaAs InGaP etch stop InAlAs barrier Approach #2: Don’t Grow It Quasi-Selective growth Wistey EMC 2009 M. Wistey, Spring ECS 2009 24 Regrowth on InP vs. InGaP InP regrowth RHEED InP regrowth SEM SEM: U. Singisetti • Conversion of <6nm InP to InAs • Strain relaxation As P InGaAs InAs InGaAs InAs InP etch stop InAlAs barrier InAlAs barrier As M. Wistey, Spring ECS 2009 25 Regrowth on InGaP As • Replace InP with InGaP • Converts to InGaAs (good!) • Strain compensation Wistey EMC 2008 Converted from InGaP P InGaAs InGaP InGaAs InGaP InGaAs InGaP InAlAs barrier InGaP regrowth RHEED InGaP regrowth SEM 2 M. Wistey, Spring ECS 2009 26 DEPLETION-MODE MOSFETS 27 SiNx Scalable InGaAs MOSFETs 300 nm SiO2 Cap 50 nm Cr 50 nm W Mo Mo 5 nm Al2O3 ++ n regrowth InGaAs Channel, NID n++ regrowth 3 nm InGaP Etch Stop, NID 10 nm InAlAs Setback, NID 5 nm InAlAs, Si=8x1019 cm-3 200 nm InAlAs buffer Semi-insulating InP Substrate Top view SEM M. Wistey, Spring ECS 2009 Oblique view 28 SiNx Scalable InGaAs MOSFETs 300 nm SiO2 Cap 50 nm Cr 50 nm W Mo Mo 5 nm Al2O3 ++ n regrowth InGaAs Channel, NID n++ regrowth 3 nm InGaP Etch Stop, NID 10 nm InAlAs Setback, NID 5 nm InAlAs, Si=8x1019 cm-3 200 nm InAlAs buffer Semi-insulating InP Substrate • Conservative doping design: • [Si] = 4x1013 cm-2 • Bulk n = 1x1013 cm-2 >> Dit • Large setback + high doping = Can’t turn off 0.9µm 0.8µm 0.7µm 0.6µm 0.5µm 0.5µm 1µm 10µm M. Wistey, Spring ECS 2009 29 SiNx Series Resistance 300 nm SiO2 Cap Possible causes: Poly nucleation at gate Thinning near gate Strain-induced dislocations Incomplete underfill Insufficient doping under sidewall Now known to be a growth issue. See DRC & EMC 2009 for solution. 50 nm Cr 50 nm W Mo 5 nm Al2O3 ++ n regrowth InGaAs Channel, NID 3 nm InGaP Etch Stop, NID 10 nm InAlAs Setback, NID 5 nm InAlAs, Si=8x1019 cm-3 InAlAs buffer M. Wistey, Spring ECS 2009 30 The Shape of Things to Come Generalized Self-Aligned Regrowth Designs: Recessed n+ Regrowth Raised Gate Gate Top Barrier Top Barrier Channel Back Barrier Substrate Channel Back Barrier Substrate • Self-aligned regrowth can also be used for: • GaN HEMTs (with Mishra group at UCSB) • GaAs pMOS FETs • InGaAs HBTs and HEMTs • All high speed III-V electronics M. Wistey, Spring ECS 2009 31 Conclusions • Scaled III-V CMOS requires more than reduced dimensions • InGaAs offers a high velocity channel, high mobility access • Self-aligned regrowth: a roadmap for scalable III-V FETs –Provides III-V’s with a salicide equivalent –Can improve GaN and GaAs FETs too • DFETs show peak gm = 0.24mS/µm • High resistance (a growth problem) limited FET performance M. Wistey, Spring ECS 2009 32 Acknowledgements • Rodwell & Gossard Groups (UCSB): Uttam Singisetti, Greg Burek, Ashish Baraskar, Vibhor Jain... • McIntyre Group (Stanford): Eunji Kim, Byungha Shin, Paul McIntyre • Stemmer Group (UCSB): Joël Cagnon, Susanne Stemmer • Palmstrøm Group (UCSB): Erdem Arkun, Chris Palmstrøm • SRC/GRC funding • UCSB Nanofab: Brian Thibeault, NSF M. Wistey, Spring ECS 2009 33 Conclusions • Scaled III-V CMOS requires more than reduced dimensions • InGaAs offers a high velocity channel, high mobility access • Self-aligned regrowth: a roadmap for scalable III-V FETs –Provides III-V’s with a salicide equivalent –Can improve GaN and GaAs FETs too • DFETs show peak gm = 0.24mS/µm • High resistance (a growth problem) limited FET performance M. Wistey, Spring ECS 2009 34