2008 Indium Phosphide and Related Materials Conference, May, Versailles, France Technology Development & Design for 22 nm InGaAs/InP-channel MOSFETs M.
Download ReportTranscript 2008 Indium Phosphide and Related Materials Conference, May, Versailles, France Technology Development & Design for 22 nm InGaAs/InP-channel MOSFETs M.
2008 Indium Phosphide and Related Materials Conference, May, Versailles, France Technology Development & Design for 22 nm InGaAs/InP-channel MOSFETs M. Rodwell University of California, Santa Barbara M. Wistey, U. Singisetti, G. Burek, A. Gossard, S. Stemmer, R. Engel-Herbert, Y. Hwang, Y. Zheng, C. Van de Walle University of California Santa Barbara P. Asbeck, Y. Taur, A. Kummel, B. Yu, D. Wang, Y. Yuan, University of California San Diego [email protected] 805-893-3244, 805-893-5705 fax C. Palmstrøm, E. Arkun, P. Simmonds University of Minnesota P. McIntyre, J. Harris, Stanford University M. V. Fischetti, C. Sachs University of Massachusetts Amherst Specific Acknowledgements ( Device Team ) Dr. Mark Wistey Uttam Singisetti Prof. Chris Palmstrøm CBE Regrowth Greg Burek Dr. Erdem Arkun Lead: Device Development MBE Regrowth Why III-V CMOS ? Why Develop III-V MOSFETs ? Silicon MOSFETs continue to scale... ...22 nm is feasible in production ( or so the Silicon industry tells us...) ...16 nm ? -- it is not yet clear If we can't make MOSFETs yet smaller, instead move the electrons faster: Id / Wg = qnsv Id / Qtransit = v / Lg III-V materials→ lower m*→ higher velocities Serious challenges: High-K dielectrics on InGaAs channels, InGaAs growth on Si True MOSFET fabrication processes Designing small FETs which use big (low m*) electrons Simple FET Scaling Goal: double transistor bandwidth when used in any circuit → reduce 2:1 all capacitances and all transport delays → keep constant all resistances, voltages, currents All lengths, widths, thicknesses reduced 2:1 S/D contact resistivity reduced 4:1 Cgd / Wg ~ gm / Wg ~ v / Tox Cgs / Wg ~ Lg / Tox Cgs, f / Wg ~ Csb / Wg ~ Lc / Tsub If Tox cannot scale with gate length, Cparasitic / Cgs increases, gm / Wg does not increase hence Cparasitic /gm does not scale FET scaling: Output Conductance & DIBL ( Cgs expressionneglectsthe effect of a finitedensityof states ) Cgs ~ Wg Lg / Tox Id Q / Cd ch ~ Wg where Q CgsVgs Cd chVds transconductance output conductance → Keep Lg / Tox constant as we scale Lg Well-Known: Si FETs No Longer Scale Perfectly Effective oxide thickness is no longer scaling in proportion to Lg (ITRS roadmap copied from Larry Larson's files) High - K gate dielectrics : SiO 2 interlayerlimits acheivable ( capacitance / area ) Gate capacitance densityis not increasingrapidly Output conductance is degrading C /I d is improvingonlyslowly ...soon will dominategate delay parasitic Highly Scaled MOSFETs: What Are Our Goals ? Low off-state current (10 nA/mm) for low static dissipation → minimum subthreshold slope→ minimum Lg / Tox low gate tunneling, low band-band tunneling Low delay CFET DV/I d in gates where transistor capacitances dominate. Parasitic capacitances are 0.5-1.0 fF/mm → while low Cgs is good, high Id is much better Low delay Cwire DV/Id in gates where wiring capacitances dominate. large FET footprint → long wires between gates → need high Id / Wg ; target ~6 mA/mm short transit time alone (low Cgs, int DVgs/DId ) is not sufficient III-V MOSFETs: Drive Current and CV/I delay III-V CMOS: The Benefit Is Low Mass, Not High Mobility Simple drift - diffusion theory,nondegenerate,far above threshold: I D coxWg vinjection(Vgs Vth DV ) where vinjection ~ vthermal (kT / m* )1/2 Id DV vinjectionLg / m Ensure thatDV (Vgs Vth ) ~ 700 mV Vth Vgs low effective mass → high currents mobilities above ~ 1000 cm2/V-s of little benefit at 22 nm Lg Low Effective Mass Impairs Vertical Scaling Shallow electron distribution needed for high gm / Gds ratio, low drain-induced barrier lowering. 2 . Energy of Lth well state ~ L2 / m*Twell For thin wells, only 1st state can be populated. For very thin wells, 1st state approaches L-valley. Only one vertical state in well. Mimimum ~ 5 nm well thickness. → Hard to scale below 22 nm Lg. Density-Of-States Capacitance E f Ewell ns /(nm* / 22 ) V f Vwell s / cdos where cdos q2nm* / 22 and n is the # of band minima Two implications: - With Ns >1013/cm2, electrons populate satellite valleys Fischetti et al, IEDM2007 - Transconductance dominated by finite state density Solomon & Laux , IEDM2001 Drive Current in the Ballistic & Degenerate Limits More careful analyses by Taur & Asbeck Groups, UCSD; Fischetti Group: U-Mass: IEDM2007 Drive Current in the Ballistic & Degenerate Limits mA Vgs Vth J K 84 mm 1 V 3/ 2 , where K n m* mo 1 (c 1/ 2 * dos ,o / cox ) n ( m / mo ) 0.3 n=1 0.25 EOT=0.2 nm eot includes the electron wavefunction depth K 0.2 0.4 nm 0.15 0.6 nm 0.1 0.05 0 0.01 1 nm 0.1 m*/mo Inclusive of non-parabolic band effects, which increase cdos , InGaAs & InP have near-optimum mass for 0.4-1.0 nm EOT gate dielectrics 1 3/ 2 Rough Projections From Simple Ballistic Theory 22 nm gate length Channel EOT 0.5-1.0 fF/mm parasitic capacitances drive current (700 mV overdrive) intrinsic gate capacitance InGaAs InGaAs 1 nm 1/2 nm 6 mA/mm 8.5 mA/mm 0.2 fF/mm 0.25 fF/mm Si Si 1 nm 1/2 nm 2.5-3.5 mA/mm 5-7 mA/mm 0.7 fF/mm 1.4 fF/mm InGaAs has much less gate capacitance 1 nm EOT → InGaAs gives much more drive current 1/2 nm EOT → InGaAs & Si have similar drive current InGaAs channel→ no benefit for sub-22-nm gate lengths Device Structure & Process Flow Device Fabrication: Goals & Challenges III-V HEMTs are built like this→ Source Gate Drain K Shinohara ....and most III-V MOSFETs are built like this→ Device Fabrication: Goals & Challenges Yet, we are developing, at great effort, a structure like this → N+ source regrowth r TiW r InGaAs well InP well barrier Why ? Source Gate K Shinohara Drain N+ drain regrowth Why not just build HEMTs ? Gate Barrier is Low ! Gate barrier is low: ~0.6 eV Source Gate Drain K Shinohara Tunneling through barrier → sets minimum thickness Emission over barrier → limits 2D carrier density Ec EF Ec EF Ewell- Ewell- At Ns 1013 / cm2 , (E f Ec ) ~ 0.6 eV Why not just build HEMTs ? Gate barrier also lies under source / drain contacts Source Gate Drain N+ layer widegap barrier layer K Shinohara low leakage: need high barrier under gate low resistance: need low barrier under contacts Ec EF Ec EF Ewell- N+ cap layer Ewell- The Structure We Need -- is Much Like a Si MOSFET sidewall gate dielectric metal gate source contact N+ source drain contact N+ drain quantum well / channel barrier substrate no gate barrier under S/D contacts high-K gate barrier Overlap between gate and N+ source/drain How do we make this device ? Source/Drain Implantation Does Not Look Easy implantation implantation metal gate source contact drain contact InGaAs quantum well barrier substrate Implantation will intermix InGaAs well & InAlAs barrier Annealing can't fix this. Incommensurate sublimation of III vs. V elements during anneal Need ~ 5 nm implant depth & ~ 6*1019 /cm3 doping Implanted structures have not shown the necessary low contact resistivity. So, We Are Forming the Source/Drain By Regrowth Process selected to meet 22 nm ITRS targets metal gate InGaAs quantum well barrier But... substrate unlike HEMT process flows, fully established in 1980's... metal gate InGaAs quantum well barrier ...most process steps here are completely new substrate sidewall metal gate N+ source InGaAs quantum well N+ drain barrier substrate gate dielectric sidewall metal gate source contact N+ source drain contact InGaAs quantum well barrier substrate N+ drain The technology is aggressive and challenging The Required Performance is Formidable ~5 nm thick well 1 nm Insulator EOT Target ~7 mA/mm @ 700 mV gate overdrive sidewall gate dielectric metal gate source contact N+ source drain contact quantum well / channel N+ drain barrier substrate For 10%impacton drive current, I D RS 70 mV. (20 nm N extension) (100 / square) 2 mm Rs 10 mm (0.25 mm2 ) /(25 nm wide contact) 10 mm Process Development Process Flow with MBE Source/Drain Regrowth Process Flow with MBE Source/Drain Regrowth Gate Dielectrics ALD Al2O3 from IBM (D. Sedana) & Stanford (P. McIntyre) ALD ZrO2 from Intel (S. Koveshnikov et al, DRC 2008) Al2O3 is more robust in processing. → initial process development Process modules being developed for ZrO2 . Gate Definition: Challenges rea S/D regrowth r Must scale tor22 nm r r Dielectric cap on gate for source/drain regrowth r well InP well barrier CBE in-situ etch Metal & Dielectric etch must stop in 5 nm channel r r r Semiconductor through 5 nm InP subchannel well etch must not etchwell well InP well InP for wellS/D regrowth InP well Process must leave surfaces ready barrier CBE selective-area regrowth barrier in-situ S/D metal deposition barrier planarize & etch Gate Stack: Multiple Layers & Selective Etches Key: stop etch before reaching dielectric, then gentle low-power etch to stop on dielectric Sidewall Formation r r r r well barrier r well barrier r well barrier (starting material) PECVD Si3N4 PECVD SiN sidewall deposition, low power anisotropic RIE etch ICP RIE etch CF4 / O2 ...sidewall etch must not damage the channel Clean, Undamaged Surface Before Regrowth undamaged InP subchannel (after Al2O3 dielectric etch & InGaAs recess etch ) Two Source/Drain Regrowth Processes non-selective-area S/D regrowth non-selective-area S/D regrowth non-selective area S/D regrowth by Molecular Beam Epitaxy: Wistey r r r r r r InGaAs InGaAs well well InP well InP well r r well well InP InP well well r r well well InP InP well well barrier barrier barrier barrier barrier barrier r r (starting (starting material) material) recess recess etch etch nonselective regrowth regrowth nonselective in-situ S/D S/D metal metal in-situ planarize planarize r r r r r r r r well well InP InP well well r r well well InP InP well well r r well well InP InP well well barrier barrier barrier barrier barrier barrier etch etch strip strip planarization planarization material material electroplate electroplate S/D metal metal S/D selective area S/D S/D regrowth by Chemical Beam Epitaxy: Palmstrøm / Arkun selective-area regrowth rr rr rr rr rr rr r r InGaAs InGaAs well well InP well InP well r r well well InP InP well well r r well well InP InP well well r r well well InP InP well well r r well well InP InP well well r r well well InP InP well well barrier barrier barrier barrier (starting (starting material) material) CBE CBE in-situ in-situ etch etch barrier barrier CBE CBE selective-area selective-area regrowth regrowth barrier barrier in-situ in-situ S/D S/D metal metal deposition deposition barrier barrier planarize planarize & & etch etch barrier barrier electroplate electroplate S/D S/D metal metal non-selective-area S/D regrowth Recess Etch & Regrowth: Inter-Relationships selective-area S/D regrowth non-selective regrowth selective CBE regrowth r r r r r r InGaAs well InP well barrier wellInGaAs well InP well InP well barrier barrier r or r r rr r r rr well well InPwell well InP barrier barrier r wellwell InP InP wellwell barrier barrier InGaAs/InP composite (starting material) recesschannel etch planarize (starting material) CBE in-situ etch CBEetch nonselective regrowth selective-area permits selective InGaAs wet-etch, stopping on InP in-situ S/D metal regrowth regrowth initiated on InP (desirable ?) wel InP w barrie s in-situ S/D m metal deposition If regrowth can extend laterally under sidewall, sidewall can be thicker Regrowth interface resistance In addition to the contact & link resistances sidewall gate dielectric metal gate source contact N+ source drain contact InGaAs channel N+ drain InP sub-channel barrier substrate resistance at the regrowth interfaces is also of concern... Contact & Regrowth Interface Resistance Selective -Arkun Nonselective -Wistey 14 N+ RG 12 r r r well well InP well barrier InP well barrier N+ InGaAs TLM B SI InP 10 Resistance () r Mo contact Mo contact 0.8 - mm2 0.5 - mm2 8 Mo contact 6 TLM A Mo contact N+ RG N+ InGaAs SI InP 4 2 0 0 5 10 15 Pad Spacing (mm) 20 25 30 TEM of Regrowth: InGaAs on InGaAs (Mark Wistey) HRTEM InGaAs n+ regrowth Interface HAADF-STEM` InGaAs n+ Interface 2 nm Images of MBE Regrowth (dummy sample) Regrowth process is still being de-bugged growth on sidewall: bad ! to suppress, grow hotter lateral regrowth under gate: good ! Oxide TiW Planarization / Etch-Back Process Ashed-back PR covers S/D contacts Mo etched in SF6/Ar dry etch PR strip removes polymers. Mo protects semiconductor from descum plasma. Images of Completed Device Results & Status 1st working devices: (ISCS submission) MBE S/D regrowth incomplete S/D growth under gate → high access resistance → low drive current (1 mA/mm !) Cause of Problems related to regrowth on InP subchannel has impacted both MBE & CBE regrowth ...and is now resolved New devices now in fabrication...stay tuned InGaAs/InP Channel MOSFETs for VLSI Low-m* materials are beneficial only if EOT cannot scale below ~1/2 nm Devices cannot scale much below 22 nm Lg→ limits IC density Little CV/I benefit in gate lengths below 22 nm Lg Need device structure with very low access resistance radical re-work of device structure & process flow Gate dielectrics, III-V growth on Si: also under intensive development