Transcript The Development of Large-Area PsecResolution TOF Systems Henry Frisch Enrico Fermi Institute and Physics Dept University of Chicago With Harold Sanders, and Fukun Tang (EFI-EDG)

The Development of
Large-Area PsecResolution TOF Systems
Henry Frisch
Enrico Fermi Institute and Physics Dept
University of Chicago
With Harold Sanders, and Fukun Tang (EFI-EDG) Karen
Byrum and Gary Drake (ANL); Tim Credo (IMSA, now
Harvard), Shreyas Bhat, and David Yu (students)
11/6/2015
HJF DOE Review
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What is the intrinsic limit
for TOF for rel. particles?
Typical path lengths for light and electrons are set by
physical dimensions of the light collection and amplifying device.
These are now on the order of an inch. One inch is 100 psec. That’s what
we measure- no surprise! (pictures swiped from T. Credo talk at Workshop)
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Major advances for TOF measurements:
Microphotograph of
Burle 25
micron tubeGreg Sellberg
(Fermilab)
1. Development of MCP’s with 6-10 micron
pore diameters
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Major advances for TOF measurements:
Output at anode
from simulation of
10 particles going
through fused
quartz window- T.
Credo, R. Schroll
Jitter on
leading
edge 0.86
psec
2. Ability to simulate electronics and systems
to predict design performance
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Major advances for TOF measurements:
Simulation
with IHP
Gen3 SiGe
processFukun Tang
(EFI-EDG)
3. Electronics with typical gate jitters << 1 psec
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Geometry for a Collider Detector
2” by 2” MCP’s
Beam Axis
Coil
“r” is expensive- need a thin segmented detector
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Generating the signal
Use Cherenkov light - fast
A 2” x 2” MCPactual thickness
~3/4”
e.g. Burle
(Photonis) 85022with mods per
our work
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Anode Structure
1. RF Transmission
Lines
2. Summing smaller
anode pads into 1” by
1” readout pixels
3. An equal time summake transmission
lines equal
propagation times
4. Work on leading
edge- ringing not a
problem for this fine
segmentation
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Tim’s Equal-Time Collector
Equal-time transmissionline traces to output pin
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4 Outputseach to a
TDC chip
(ASIC)
Chip to have
< 1psec
resolution(!)
-we are
doing this in
the EDG
(Harold,
Tang).
9
Dummy 1
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Anode Return Path Problem
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Solving the return-path problem
2 in.
0.070
0.250
0.160
Capacitive Return Path
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Mounting electronics on
back of MCP- matching
Conducting
Epoxy- machine
deposited by
Greg Sellberg
(Fermilab)
dum
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EDG’s Unique Capabilities Harold’s Design for Readout
Each module has
5 chips- 4 TDC
chips (one per
quadrant) and a
DAQ `mother’
chip.
Problems are
stability,
calibration, rel.
phase, noise.
Both chips are
underway
dum
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Tang’s work in IHP (200 GHz) design tools
dum
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Requirement: Psec-Resolution TDC
Tang Slide
MCP_PMT Output Signal
Start
Reference Clock
Stop
500pS
Tw
1 ps Resolution Time-to-Digital Converter!!!
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Approaches & Possibilities
(2) Time Stretcher
1/4
“Zero”-walk Disc.
Receiver
Stretcher
Driver
Tang Slide
11-bit Counter
PMT
CK5Ghz
2 Ghz PLL
REF_CLK
psFront-end (Timing Module Option #2)
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Time Stretcher: Simulation Result
Tang Slide
x200 Stretched Time Interval
(Output Signal )
Stretched Time = 274ns
(pedestal=74ns)
1ns Time Interval (Input Signal)
0
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50ns
100ns
150ns
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200ns
250ns
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300ns
VCO: Submission of Oct. 2006
Ultimate Goal:

To build TDC with 1 pSec Resolution for Large Scale of Time-of-Flight
Detector.
Primary Goal:



To build 2-Ghz VCO, key module of PLL that generates the TDC reference
signal
 Cycle-to-Cycle Time-jitter < 1 ps
To evaluate IHP SG25H1/M4M5 Technology for our applications
To gain experiences on using Cadence tools (Virtuoso Analog Environment)
 Circuit Design (VSE)
 Simulation (Spectre)
 Chip Layout (VLE, XLE, VCAR)
 DRC and LVS Check (Diva, Assura, Calibre)
 Parasitic Extraction (Diva)
 Post Layout Simulation (Spectre)
Tang Slide
 GDSII Stream out
 Validation
 Tape Out
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Diagram of Phase-Locked Loop
Tang Slide
Fref
CP
I1
PD
Uc
LF
VCO
F0
I2
1
N
PD: Phase Detector
CP: Charge Pump
LF: Loop Filter
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VCO:
Voltage
Controlled Oscillator21
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IHP (SG25H1) 0.25mm SiGe
BiCMOS Technology
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0.25mm BiCMOS technology
200Ghz NPN HBT (hetero-junction bipolar
transistor)
MIM Capacitors (layer2-layer3) ( 1f/1u2 )
Inductors (layer3-layer4)
High dielectric stack for RF passive component
5 metal layers (Al)
Digital Library: Developing
Tang Slide
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Tang Slide
SG25 Process Specification
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Tang Slide
2-GHz BiCMOS VCO Schematic
Negative Resistance and Current-Limited Voltage
Control Oscillator with Accumulating PMOS Varicap
and 50W Line Drivers
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V-F Plot (3 model cases @ 27C-55C)
Frequency
Tang Slide
Temperature: 27C-55C
Supply:
VDD=2.5V
VControl varied 0.18V
VControl
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Phase Noise ( 3 model cases @ 27C)
@100KHz offset
Tang Slide
Worst
Best
Typical
Worst
Typical
-89.94 dBc/Hz
-89.58 dBc/Hz
-89.90 dBc/Hz
Best
Tang Slide
Temperature: 27C
Supply:
VDD=2.5V
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Calculation of Cycle-to-Cycle Jitter
Tang Slide
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Virtuoso XL Layout View
Tang Slide
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Virtuoso Chip Assembly Router View
Tang Slide
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Transit Analysis: Comparison of Schematic and
Post Layout Simulations
Outputs@50W loads
Schematic
Post Layout
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Tang Slide
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Simulation for Coil Showering and
various PMTs (Shreyas Bhat)
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Right now, we have a simulation using GEANT4, ROOT,
connected by a python script
GEANT4: pi+ enters solenoid, e- showers
ROOT: MCP simulation - get position, time of arrival of
charge at anode pads
Both parts are approximations
Could we make this less home-brew and more modular?
Could we use GATE (Geant4 Application for Tomographic
Emission) to simplify present and future modifications?
Working with Prof. Chin-tu Chen and students, UCHospitals
Radiology- they know GATE very well, use it regularly
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Possible Collider Applications
•Separating b from b-bar in measuring the top mass (lessens
combinatorics)
•Identifying csbar and udbar modes of the W to jj decays in
the top mass analysis (need this once one is below 1 GeV, I
believe)
•Separating out vertices from different collisions at the LHC
in the z-t plane
•Identifying photons with vertices at the LHC (requires
spacial resolution and converter ahead of the TOF system
• Locating the Higgs vertex in H to gamma-gamma at the
LHC (mass resolution)
•Kaon ID in same-sign tagging in B physics (X3 in CDF Bs
mixing analysis)
•Fixed target geometries- LHCb, Diffractive LHC Higgs,
(and rare K and charm FT experiments)
•Super-B factory (Nagoya Group, V’avra at SLAC)
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Synergies- The ILC, Radiology
ANL,Fermilab,SLAC, BSD,Saclay,
Photonis
•ILC- met with Fermilab last week to discuss possible ILC
applications- have propsed a workshop with them to
explore physics of particle ID at the ILC
•Positron-Emission Tomography – have a draft of a
proposal to UC for a program for applying HEP techniques
to radiology -with Chin-Tu Chen, Radiology
Have agreed to write MOU with Saclay (Patrick LeDu)
Have agreed to write MOU with Photonis/Burle to
develop new MCPs optimized for timing
We are working with Jerry V’avra (SLAC) on measurement
setups (Karen and Gary at ANL have the setup).
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Status
1. Have a simulation of Cherenkov radiation in MCP into electronics
2. Have placed an order with Burle- have the 1st of 4 tubes and have a
good working relationship (their good will and expertise is a major
part of the effort): 10 micron tube in the works; optimized versions
discussed
3. Have licence and tools from IHP working on our work stationsTang is adept and fast working with them. Excellent support from
Cadence.
4. Have modeled DAQ/System chip in Altera (Jakob Van Santen: Sr)
5. ANL has put together a test stand with working DAQ, has bought a
very-fast laser, has made contact with advanced accel
folks:(+students)
6. Have established strong working relationship with Chin-Tu Chen’s
PET group at UC; source of good students; common interests (with
Saclay too). Hope can establish a program in the application of HEP
to meds
7. Harold and Tang have a good grasp of the overall system problems
and scope, and have a top-level design plus details
8. Have found Greg Sellberg at Fermilab to offer expert precision
assembly advice and help (wonderful tools and talent!).
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Review (SLAC); will work with Saclay
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9. Are
working closely with Jerry
V’avra
This was the text on my penultimate slide at
the workshop at Arlington TX in April
Next Steps
1. Start testing the MK-0 device we have (ANL)
2. Understand the electrical circuit in the MCP and
specify the next model (MK-I) we want
3. Finish the design and place the order to IHP for the
1st chip.
THE END (not really)
Substantial Progress on all 3
See hep.uchicago.edu/~frisch
For more documents and links
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The Electronics Development Group
of the EFI

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Over a million dollars of software tools
from a number of vendors- built up by
Harold. Nowhere else I know of…
Major impact on CDF,Atlas, KTeV, Quiet,
…
Serves not just UC- other institutions send
folks here- systems are collaborative
Student involvement- we train students in
cutting-edge electronics (grad and underg)
Highly innovative designs 11/6/2015
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DOE-ADR Funds

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First chip submission was last week-ADR
Tang leaves tomorrow for Germany for
IHP Workshop-ADR
Starting on next submission design…
Will seed collaborative work with ANL,
SLAC (V’avra), and, hopefully, Fermilab
Would like to discuss longer-term support
for a program of Applications of HEP
Techniques to Radiology, and also some
EDG support.
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Backup Slides
Miscellaneous…..
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Got Burle MK-0 (our name)- many
thanks!

Paul Mitchell has done nice things- wonderful test bed for
understanding
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V-F Plot: Comparison of Schematic and Post
Layout Simulations
Frequency
Post Layout
Schematic
Vcontrol
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Phase Noise: Post Layout Simulations
VDD=2.5V Temp.=27C, 55C
Phase Noise @100KHZ offset
27C
55C
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-89.40 dBc/Hz
(Sch: -89.75)
-88.90 dBc/Hz
(Sch: -89.15)
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A real CDF event- r-phi view
Key idea- fit t0 (start) from all tracks
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Conclusion
(1) VCO time-jitter met our requirement.
(2) Post layout simulation matched
schematic simulation very well.
(3) Some problems we have encountered
with pcell library, layout, DRC, LVS and
auto-routing functionalities.
(4) Ready for October Submission.
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Shreyas Bhat slide
Input Source code, Macros Files
•Geometry
•Materials
•Particle:
•Type
•Energy
•Initial Positions, Momentum
•Physics processes
•Verbose level
•Need to redo geometry
(local approx.➔ cylinder)
•Need to redo field
•Need to connect two
modules (python script in place
π+ Generation, Coil
Showering
GEANT4
Have position,
time, momentum,
kinetic energy of
each particle for each step
(including upon entrance to PMT)
PMT/MCP
GEANT4 - swappable
for older simulation)
Pure GEANT4
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Get HJF
position,
time
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Shreyas Bhat slide
Input Macros Files - precompiled
source
•Geometry
•Materials
•Particle:
•Type
•Energy
•Initial Positions, Momentum
•Verbose level
π+ Generation
GATE
Physics processes
macros file
Solenoid Showering
GATE
But, we need to write
Source code for
Magnetic Field, recompile
PMT/MCP
GATE - swap with
default “digitization”
module
GATE
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Get HJF
position,
time
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The Hard Parts- Reality
1. Haven’t yet plugged in a device- all simulation
2. Harold and Paul Mitchell (Burle) have taught us that the hard
part is the return path from MCP-OUT to the Gd
3. Haven’t yet submitted a design to IHP- don’t know the
realities of making chips (in progress as we speak)
4. Have no equipment to test these chips when we get them
5. Have no experience on how to measure device performance
when we actually get them.
6. We are a small group- lots to do!
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