VLSI Design Circuits & Layout

Outline  CMOS Gate Design  Pass Transistors  CMOS Latches & Flip-Flops  Standard Cell Layouts  Stick Diagrams

CMOS Gate Design  A 4-input CMOS NOR gate A B C D Y

Complementary CMOS  Complementary CMOS logic gates  nMOS

pull-down network

 pMOS

pull-up network

 a.k.a. static CMOS inputs pMOS pull-up network nMOS pull-down network Pull-down OFF Pull-up OFF Z (float) Pull-down ON 0 Pull-up ON 1 X (crowbar) output

Series and Parallel     nMOS: 1 = ON pMOS: 0 = ON

Series

: both must be ON

Parallel

: either can be ON (a) a g1 g2 b (b) a g1 g2 b a g1 b (c) g2 a g1 g2 b (d) 0 a 0 b OFF 0 a 0 b ON 0 a 1 b OFF 0 a 1 b OFF 1 a 0 b OFF 1 a 0 b OFF 1 a 1 b ON 1 a 1 b OFF a a 0 b OFF 0 0 b ON 1 a a 1 b ON 0 1 b ON 1 a a a a 0 b ON 0 0 b ON 1 1 b ON 0 1 b OFF 1

Conduction Complement  Complementary CMOS gates always produce 0 or 1  Ex: NAND gate    Series nMOS: Y=0 when both inputs are 1 Thus Y=1 when either input is 0 Requires parallel pMOS A B Y  Rule of

Conduction Complements

  Pull-up network is complement of pull-down Parallel -> series, series -> parallel

Compound Gates  

Compound gates

can do any inverting function Ex: AND-AND-OR-INV (AOI22)

Y

 (

A

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B

)  (

C



D

) (a) A B (c) A (e) C A A B C D B C D B C D Y D (b) A B (d) C A (f) A B C D C D D B Y

Example: O3AI 

Y

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A

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B

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C

) 

D

Example: O3AI 

Y

 (

A

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B



C

) 

D

A B C A B D D C Y

Pass Transistors s  Transistors can be used as switches g d s g d

Pass Transistors s  Transistors can be used as switches g d s g = 0 d s g = 1 d Input 0 g = 1 Output strong 0 1 g = 1 degraded 1 s g d s g = 0 d s g = 1 d Input 0 g = 0 Output degraded 0 g = 0 strong 1

Signal Strength 

Strength

of signal  How close it approximates ideal voltage source   V DD and GND rails are strongest 1 and 0 nMOS pass strong 0  But degraded or weak 1  pMOS pass strong 1  But degraded or weak 0   Thus NMOS are best for pull-down network Thus PMOS are best for pull-up network

Transmission Gates  Pass transistors produce degraded outputs 

Transmission gates

pass both 0 and 1 well

Transmission Gates  Pass transistors produce degraded outputs 

Transmission gates

pass both 0 and 1 well g a gb b g a gb b g = 0, gb = 1 a b g = 1, gb = 0 a b g a gb b g a gb b Input Output g = 1, gb = 0 0 strong 0 g = 1, gb = 0 1 strong 1

Tristates 

Tristate buffer

produces Z when not enabled EN A Y EN 0 0 1 1 A 0 1 0 1 Y Z Z 0 1 A EN Y EN

Nonrestoring Tristate  Transmission gate acts as tristate buffer  Only two transistors  But

nonrestoring

 Noise on A is passed on to Y (after several stages, the noise may degrade the signal beyond recognition) EN A Y EN

Tristate Inverter   Tristate inverter produces restored output Note however that the Tristate buffer  ignores the conduction complement rule because we want a Z output A EN EN Y

Tristate Inverter   Tristate inverter produces restored output Note however that the Tristate buffer  ignores the conduction complement rule because we want a Z output A A EN EN Y A Y Y EN = 0 Y = 'Z' EN = 1 Y = A

S 0 0 1 1 Multiplexers  2:1

multiplexer

chooses between two inputs D1 X X 0 1 D0 0 1 X X Y D0 D1 0 1 S Y

S 0 0 1 1 Multiplexers  2:1 multiplexer chooses between two inputs D1 X X 0 1 D0 0 1 X X Y 0 1 0 1 D0 D1 0 1 S Y

Gate-Level Mux Design 

YS

1

D

0 o a s  How many transistors are needed?

Gate-Level Mux Design 

YS

1

D

0 o a s  How many transistors are needed? 20 D1 S D0 Y D1 S D0 2 4 4 2 2 4 2 Y

Transmission Gate Mux  Nonrestoring mux uses two transmission gates

Transmission Gate Mux  Nonrestoring mux uses two transmission gates  Only 4 transistors S D0 D1 S Y S

D0 S S Inverting Mux  Inverting multiplexer  Use compound AOI22  Or pair of tristate inverters  Essentially the same thing  Noninverting multiplexer adds an inverter S D1 Y S D0 S S D1 S S Y D0 D1 0 1 S Y

4:1 Multiplexer  4:1 mux chooses one of 4 inputs using two selects

4:1 Multiplexer  4:1 mux chooses one of 4 inputs using two selects   Two levels of 2:1 muxes Or four tristates S1S0 S1S0 S1S0 S1S0 D0 D0 D1 0 1 S0 D2 D3 0 1 S1 0 1 Y D1 D2 Y D3

D Latch  When CLK = 1, latch is

transparent

 Q follows D (a buffer with a D elay)  When CLK = 0, the latch is

opaque

 Q holds its last value independent of D  a.k.a.

transparent latch

or

level-sensitive latch

CLK CLK D D Q Q

D Latch Design  Multiplexer chooses D or old Q D CLK 1 0 Old Q Q Q D CLK CLK CLK CLK Q Q

D Latch Operation D CLK = 1 Q Q D CLK = 0 CLK D Q Q Q

D Flip-flop D  When CLK rises, D is copied to Q  At all other times, Q holds its value  a.k.a.

positive edge-triggered flip-flop

,

master slave flip-flop

CLK CLK D Q Q

D Flip-flop Design  Built from master and slave D latches D CLK QM CLK CLK D CLK CLK Q CLK A “negative level-sensitive” latch QM CLK CLK CLK CLK A “positive level-sensitive” latch Q

D Flip-flop Operation QM Inverted version of D Q D CLK = 0 D QM Holds the last value of NOT(D) Q Q -> NOT(NOT(QM)) CLK = 1 CLK D Q

Race Condition  Back-to-back flops can malfunction from clock skew    Second flip-flop fires Early Sees first flip-flop change and captures its result Called

hold-time failure

or

race condition

Nonoverlapping Clocks  Nonoverlapping clocks can prevent races  As long as nonoverlap exceeds clock skew  Good for safe design  Industry manages skew more carefully instead  2 D  2  2 QM  1  1  1 Q  2  1  1  2

Gate Layout  Layout can be very time consuming   Design gates to fit together nicely Build a library of standard cells  Must follow a technology rule  Standard cell design methodology     V DD and GND should abut (standard height) Adjacent gates should satisfy design rules nMOS at bottom and pMOS at top All gates include well and substrate contacts

Example: Inverter

Layout using Electric Inverter, contd..

Example: NAND3      Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 V DD rail at top Metal1 GND rail at bottom 32  by 40 

NAND3 (using Electric), contd.

Stick Diagrams 

Stick diagrams

help plan layout quickly  Need not be to scale  Draw with color pencils or dry-erase markers

Stick Diagrams 

Stick diagrams

help plan layout quickly  Need not be to scale  Draw with color pencils or dry-erase markers VDD Vin GND Vout

Wiring Tracks  A

wiring track

 4  is the space required for a wire width, 4  spacing from neighbor = 8  pitch  Transistors also consume one wiring track

Well spacing  Wells must surround transistors by 6   Implies 12  between opposite transistor flavors  Leaves room for one wire track

Area Estimation  Estimate area by counting wiring tracks  Multiply by 8 to express in 

Example: O3AI  Sketch a stick diagram for O3AI and estimate area 

Y

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A

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B



C

) 

D

Example: O3AI  Sketch a stick diagram for O3AI and estimate area 

Y

 (

A



B



C

) 

D

Example: O3AI  Sketch a stick diagram for O3AI and estimate area 

Y

 (

A

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B

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C

) 

D