Transcript Stick Diagram

CMOS Layers



n-well process
p-well process
Twin-tub process
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n-well process
Gate
NMOS
PMOS
PMOS
NMOS
FOX
n+
n+
n+
n+
p+
p+
n-well
p-substrate
MOSFET Layers in an n-well process
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p+
p+
Layer Types







p-substrate
n-well
n+
p+
Gate oxide
Gate (polycilicon)
Field Oxide


Insulated glass
Provide electrical isolation
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Top view of the FET pattern
NMOS
n+
n+
PMOS
NMOS
n+
n+
p+
PMOS
p+
n-well
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p+
p+
Metal Interconnect Layers


Metal layers are electrically isolated from
each other
Electrical contact between adjacent
conducting layers requires contact cuts and
vias
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Metal Interconnect Layers
Ox3
Via
Metal2
Active
contact
Ox2
Metal1
Ox1
n+
n+
n+
p-substrate
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n+
CMOS Gate Design

A 4-input CMOS NOR gate
A
B
C
D
Y
Complementary CMOS

Complementary CMOS logic gates



nMOS pull-down network
pMOS pull-up network
a.k.a. static CMOS
pMOS
pull-up
network
inputs
output
nMOS
pull-down
network
Pull-up OFF
Pull-up ON
Pull-down OFF
Z (float)
1
Pull-down ON
0
X (crowbar)
Series and Parallel
a
a
0
g1
g2
(a)



nMOS: 1 = ON
pMOS: 0 = ON
Series: both must be ON
Parallel: either can be ON
g2
OFF
OFF
ON
a
a
a
a
0
0
1
1
0
1
0
1
b
(d)
b
b
b
b
ON
OFF
OFF
OFF
a
a
a
a
0
0
0
1
1
0
1
1
b
b
b
b
OFF
ON
ON
ON
a
a
a
a
a
g2
1
OFF
b
g1
0
b
a
(c)
1
1
b
(b)
g2
1
b
b
g1
a
b
a
g1
a
0
0
b

a
0
0
0
1
1
0
1
1
b
b
b
b
ON
ON
ON
OFF
Conduction Complement

Complementary CMOS gates always produce 0 or 1

Ex: NAND gate



Series nMOS: Y=0 when both inputs are 1
Thus Y=1 when either input is 0
Requires parallel pMOS
Y
A
B

Rule of Conduction Complements


Pull-up network is complement of pull-down
Parallel -> series, series -> parallel
Compound Gates

Compound gates can do any inverting function

Ex: AND-AND-OR-INV (AOI22)
Y  ( A  B)  (C  D)
A
C
A
C
B
D
B
D
(a)
A
(b)
B C
D
(c)
D
A
B
(d)
C
D
A
B
A
C
B
D
A
B
C
D
Y
(e)
C
(f)
Y
Example: O3AI

Y  ( A  B  C)  D
Example: O3AI

Y  ( A  B  C)  D
A
B
C
D
Y
D
A
B
C
Pass Transistors

Transistors can be used as switches
g
s
d
g
s
d
Pass Transistors

Transistors can be used as switches
g=0
g
s
d
s
d
Input g = 1 Output
0
strong 0
g=1
s
g=0
g
s
d
d
s
1
Input
d
g=1
s
g=1
d
degraded 1
g=0
0
Output
degraded 0
g=0
strong 1
Signal Strength

Strength of signal



VDD and GND rails are strongest 1 and 0
nMOS pass strong 0



But degraded or weak 1
pMOS pass strong 1


How close it approximates ideal voltage source
But degraded or weak 0
Thus NMOS are best for pull-down network
Thus PMOS are best for pull-up network
Transmission Gates


Pass transistors produce degraded
outputs
Transmission gates pass both 0 and 1 well
Transmission Gates


Pass transistors produce degraded
outputs
Transmission gates pass both 0 and 1 well
Input
g
a
b
gb
a
b
gb
g = 0, gb = 1
a
b
g = 1, gb = 0
0
strong 0
g = 1, gb = 0
a
b
g = 1, gb = 0
strong 1
1
g
g
a
g
b
gb
Output
a
b
gb
Tristates

Tristate buffer produces Z when not
enabled
EN
EN
A
Y
0
0
Z
0
1
Z
1
0
0
1
1
1
Y
A
EN
Y
A
EN
Nonrestoring Tristate

Transmission gate acts as tristate buffer


Only two transistors
But nonrestoring
 Noise on A is passed on to Y (after several stages, the
noise may degrade the signal beyond recognition)
EN
A
Y
EN
Tristate Inverter


Tristate inverter produces restored output
Note however that the Tristate buffer

ignores the conduction complement rule because we want a
Z output
A
EN
Y
EN
Tristate Inverter


Tristate inverter produces restored output
Note however that the Tristate buffer

ignores the conduction complement rule because we want a
Z output
A
A
A
EN
Y
Y
Y
EN = 0
Y = 'Z'
EN = 1
Y=A
EN
Multiplexers

2:1 multiplexer chooses between two
inputs
S
D1
D0
0
X
0
0
X
1
1
0
X
1
1
X
S
Y
D0
0
Y
D1
1
Multiplexers

2:1 multiplexer chooses between two
inputs
S
D1
D0
Y
0
X
0
0
0
X
1
1
1
0
X
0
1
1
X
1
S
D0
0
Y
D1
1
Gate-Level Mux Design


Y

S
D

S
D
(
t
o
o
m
a
n
y
t
r
a
n
s
i
s
t
o
r
s
)
1
0
How many transistors are needed?
Gate-Level Mux Design


Y

S
D

S
D
(
t
o
o
m
a
n
y
t
r
a
n
s
i
s
t
o
r
s
)
1
0
How many transistors are needed? 20
D1
S
D0
D1
S
D0
Y
4
2
4
2
4
2
2
Y
Transmission Gate Mux

Nonrestoring mux uses two transmission
gates
Transmission Gate Mux

Nonrestoring mux uses two transmission
gates

Only 4 transistors
S
D0
S
Y
D1
S
Inverting Mux

Inverting multiplexer




D0
S
Use compound AOI22
Or pair of tristate inverters
Essentially the same thing
Noninverting multiplexer adds an inverter
S
D1
D0
D1
S
S
Y
S
S
S
Y
S
D0
0
D1
1
S
Y
4:1 Multiplexer

4:1 mux chooses one of 4 inputs using two
selects
4:1 Multiplexer

4:1 mux chooses one of 4 inputs using two
selects


Two levels of 2:1 muxes
Or four tristates
S1S0 S1S0 S1S0 S1S0
D0
S0
D0
0
D1
1
S1
D1
0
Y
Y
D2
0
D3
1
1
D2
D3
D Latch

When CLK = 1, latch is transparent


When CLK = 0, the latch is opaque


Q follows D (a buffer with a Delay)
Q holds its last value independent of D
a.k.a. transparent latch or level-sensitive latch
D
Latch
CLK
CLK
D
Q
Q
D Latch Design

Multiplexer chooses D or old Q
CLK
D
1
CLK
Q
Q
Q
D
Q
0
CLK
Old Q
CLK
CLK
D Latch Operation
Q
D
CLK = 1
CLK
D
Q
Q
Q
D
CLK = 0
Q
D Flip-flop



When CLK rises, D is copied to Q
At all other times, Q holds its value
a.k.a. positive edge-triggered flip-flop,
master-slave flip-flop
CLK
CLK
D
Flop
D
Q
Q
D Flip-flop Design
Built from master and slave D latches

CLK
CLK
CLK
CLK
QM
Latch
Latch
CLK
D
QM
D
CLK
Q
CLK
CLK
Q
CLK
A “negative level-sensitive” latch
CLK
A “positive level-sensitive” latch
D Flip-flop Operation
Inverted version of D
D
QM
Q
CLK = 0
Holds the last value of NOT(D)
D
QM
Q
Q -> NOT(NOT(QM))
CLK = 1
CLK
D
Q
Race Condition

Back-to-back flops can
malfunction from clock skew



Second flip-flop fires Early
Sees first flip-flop change
and captures its result
Called hold-time failure or
race condition
Nonoverlapping Clocks

Nonoverlapping clocks can prevent races


As long as nonoverlap exceeds clock skew
Good for safe design

Industry manages skew more carefully instead
2
1
QM
D
2
2
2
1
2
Q
1
1
1
Gate Layout

Layout can be very time consuming




Design gates to fit together nicely
Build a library of standard cells
Must follow a technology rule
Standard cell design methodology




VDD and GND should abut (standard height)
Adjacent gates should satisfy design rules
nMOS at bottom and pMOS at top
All gates include well and substrate contacts
Example: Inverter
Layout using Electric
Inverter, contd..
Example: NAND3





Horizontal N-diffusion and p-diffusion strips
Vertical polysilicon gates
Metal1 VDD rail at top
Metal1 GND rail at bottom
32  by 40 
NAND3 (using Electric), contd.
Interconnect Layout Example
Gate contact
Metal1
Metal2
Metal1
MOS
Active contact
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Designing MOS Arrays
A
B
C
y
x
A
B
C
y
x
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Parallel Connected MOS Patterning
A
x
x
B
A
X
B
X
X
y
y
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Alternate Layout Strategy
x
x
A
X
X
X
X
B
A
y
y
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B
Basic Gate Design



Both the power supply and ground are routed
using the Metal layer
n+ and p+ regions are denoted using the
same fill pattern. The only difference is the nwell
Contacts are needed from Metal to n+ or p+
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The CMOS NOT Gate
Contact
Cut
Vp
Vp
X
x
x
X
n-well
x
X
x
X
Gnd
Gnd
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Alternate Layout of NOT Gate
Vp
Vp
X
X
x
x
X
X
Gnd
x
Gnd
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x
NAND2 Layout
Vp
Vp
X
X
X
a.b
Gnd
a
a.b
b
X
X
Gnd
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a
b
NOR2 Layout
Vp
Vp
X
X
ab
Gnd
a
ab
b
X
X
a b
Gnd
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X
NAND2-NOR2 Comparison
Vp
X
X
X
X
X
Gnd
Vp
X
MOS Layout
X
X
Wiring
X
Gnd
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X
General Layout Geometry
Vp
Shared drain/
source
Individual
Transistors
Shared Gates
Gnd
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Graph Theory: Euler Path
Vp
x
Vertex
b
c
x
Edge
a
Out
y
c
y
Vertex
a
b
Gnd
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Stick Diagram
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Stick Diagrams
• Cartoon of a layout.
• Shows all components.
• Does not show exact placement, transistor sizes,
wire lengths, wire widths, boundaries, or any
other form of compliance with layout or design rules.
• Useful for interconnect visualization, preliminary layout
layout compaction, power/ground routing, etc.
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Stick Diagrams
Metal
poly
ndiff
pdiff
Can also draw
in shades of
gray/line style.
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Stick Diagrams
Buried Contact
Contact Cut
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Stick Diagrams

Stick diagrams help plan layout quickly


Need not be to scale
Draw with color pencils or dry-erase markers
Stick Diagrams
 Stick diagrams help plan layout quickly
Need not be to scale
Draw with color pencils or dry-erase markers


VDD
Vin
Vout
GND
Wiring Tracks

A wiring track is the space required for a
wire


4  width, 4  spacing from neighbor = 8 
pitch
Transistors also consume one wiring track
Well spacing

Wells must surround transistors by 6 


Implies 12  between opposite transistor flavors
Leaves room for one wire track
Area Estimation

Estimate area by counting wiring tracks

Multiply by 8 to express in 
5V
5v
Dep
Vout
Enh
Vin
0V
0V
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Stick Diagram - Example I
A
OUT
B
NOR Gate
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Stick Diagram - Example II
Power
A
Out
C
B
Ground
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Points to Ponder
• be creative with layouts
• sketch designs first
• minimize junctions but avoid long poly runs
• have a floor plan plan for input, output, power
and ground locations
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The End
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