Lecture 9: Combinational Circuit Design
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Transcript Lecture 9: Combinational Circuit Design
Lecture 9:
Combinational
Circuit Design
Outline
Bubble Pushing
Compound Gates
Logical Effort Example
Input Ordering
Asymmetric Gates
Skewed Gates
Best P/N ratio
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Example 1
module mux(input s, d0, d1,
output y);
assign y = s ? d1 : d0;
endmodule
1) Sketch a design using AND, OR, and NOT gates.
D0
S
Y
D1
S
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Example 2
2) Sketch a design using NAND, NOR, and NOT gates.
Assume ~S is available.
D0
S
Y
D1
S
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Bubble Pushing
Start with network of AND / OR gates
Convert to NAND / NOR + inverters
Push bubbles around to simplify logic
– Remember DeMorgan’s Law
Y
Y
(a)
(b)
Y
(c)
D
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Y
(d)
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Example 3
3) Sketch a design using one compound gate and one
NOT gate. Assume ~S is available.
D0
S
D1
S
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Y
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Compound Gates
Logical Effort of compound gates
unit inverter
AOI21
YA
Y A BC
Y A BC D
A
B
C
A
B
C
D
A
Y
A
A
2
1
Y
AOI22
Y
4 B
C
A
2
B
2
4
4
C
Y
1
Complex AOI
Y
A
4 B
4
C
4 D
4
A
2 C
2
B
2 D
2
Y
Y A B C D E
D
E
A
B
C
Y
B
6
C
6
A
3
D
6
E
6
E
2
A
2
D
2
2
C
B
gA = 3/3
gA = 6/3
gA = 6/3
gA = 5/3
p = 3/3
gB = 6/3
gB = 6/3
gB = 8/3
gC = 5/3
gC = 6/3
gC = 8/3
p = 7/3
gD = 6/3
gD = 8/3
p = 12/3
gE = 8/3
Y
2
p = 16/3
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Example 4
The multiplexer has a maximum input capacitance of
16 units on each input. It must drive a load of 160
units. Estimate the delay of the two designs.
H = 160 / 16 = 10 B = 1 N = 2
D0
S
Y
D1
S
D0
S
D1
S
P 224
G (4 / 3) (4 / 3) 16 / 9
F GBH 160 / 9
fˆ N F 4.2
P 4 1 5
G (6 / 3) (1) 2
F GBH 20
fˆ N F 4.5
D Nfˆ P 12.4
D Nfˆ P 14
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Y
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Example 5
Annotate your designs with transistor sizes that
achieve this delay.
8
8
8
8
25
25
25
8
8
Y
25
10
10
10
10
24
6
6
12
6
6
Y
8
8
16
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160 * (4/3) / 4.2 = 50
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160 * 1 / 4.5 = 36
9
Input Order
Our parasitic delay model was too simple
– Calculate parasitic delay for Y falling
• If A arrives latest? 2
• If B arrives latest? 2.33
2
2
A
2
B
2x
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Y
6C
2C
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Inner & Outer Inputs
Inner input is closest to output (A)
Outer input is closest to rail (B)
2
A
B
If input arrival time is known
– Connect latest input to inner terminal
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2
Y
2
2
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Asymmetric Gates
Asymmetric gates favor one input over another
Ex: suppose input A of a NAND gate is most critical
– Use smaller transistor on A (less capacitance)
A
– Boost size of noncritical input
reset
– So total resistance is same
gA = 10/9
2
2
Y
A
4/3
gB = 2
4
reset
gtotal = gA + gB = 28/9
Asymmetric gate approaches g = 1 on critical input
But total logical effort goes up
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Symmetric Gates
Inputs can be made perfectly symmetric
2
2
A
1
1
B
1
1
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Skewed Gates
Skewed gates favor one edge over another
Ex: suppose rising output of inverter is most critical
– Downsize noncritical nMOS transistor
HI-skew
inverter
unskewed inverter
(equal rise resistance)
2
A
unskewed inverter
(equal fall resistance)
2
Y
1/2
A
1
Y
1
A
Y
1/2
Calculate logical effort by comparing to unskewed
inverter with same effective resistance on that edge.
– gu = 2.5 / 3 = 5/6
– gd = 2.5 / 1.5 = 5/3
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HI- and LO-Skew
Def: Logical effort of a skewed gate for a particular
transition is the ratio of the input capacitance of that
gate to the input capacitance of an unskewed
inverter delivering the same output current for the
same transition.
Skewed gates reduce size of noncritical transistors
– HI-skew gates favor rising output (small nMOS)
– LO-skew gates favor falling output (small pMOS)
Logical effort is smaller for favored direction
But larger for the other direction
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Catalog of Skewed Gates
Inverter
NAND2
2
unskewed
1
Y
guu = 1
gdd = 1
gavg
=1
avg
A
2
B
2
2
HI-skew
2
A
Y
1/2 gu
u
gdd
gavg
avg
= 5/6
= 5/3
= 5/4
B
1
A
1
1
Y
guu = 4/3
gdd = 2/3
gavg
=1
avg
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1
A
2
B
2
4
A
4
1
guu = 4/3
gdd = 4/3
gavg
= 4/3
avg
Y
1
B
Y
2
A
1
LO-skew
2
Y
2
A
NOR2
1
B
4
A
4
guu = 5/3
gdd = 5/3
gavg
= 5/3
avg
Y
guu
gdd
gavg
avg
1/2
=1
=2
= 3/2
guu
gdd
gavg
avg
= 3/2
=3
= 9/4
2
B
A
Y
1/2
2
Y
guu = 2
gdd = 1
gavg
= 3/2
avg
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1
guu = 2
gdd = 1
gavg
= 3/2
avg
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Asymmetric Skew
Combine asymmetric and skewed gates
– Downsize noncritical transistor on unimportant
input
– Reduces parasitic delay for critical input
A
reset
Y
1
A
reset
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2
Y
4/3
4
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Best P/N Ratio
We have selected P/N ratio for unit rise and fall
resistance (m = 2-3 for an inverter).
Alternative: choose ratio for least average delay
Ex: inverter
P
– Delay driving identical inverter
A
1
– tpdf = (P+1)
– tpdr = (P+1)(m/P)
– tpd = (P+1)(1+m/P)/2 = (P + 1 + m + m/P)/2
– dtpd / dP = (1- m/P2)/2 = 0
– Least delay for P = m
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P/N Ratios
In general, best P/N ratio is sqrt of equal delay ratio.
– Only improves average delay slightly for inverters
– But significantly decreases area and power
Inverter
NAND2
2
fastest
P/N ratio
A
1.414
Y
1
gu = 1.15
gd = 0.81
gavg = 0.98
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NOR2
2
Y
A
2
B
2
B
2
A
2
Y
gu = 4/3
gd = 4/3
gavg = 4/3
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1
gu = 2
gd = 1
gavg = 3/2
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Observations
For speed:
– NAND vs. NOR
– Many simple stages vs. fewer high fan-in stages
– Latest-arriving input
For area and power:
– Many simple stages vs. fewer high fan-in stages
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