Transcript Document
Introduction to
CMOS VLSI
Design
Lecture 8:
Combinational Circuits
David Harris
Harvey Mudd College
Spring 2004
Outline
Bubble Pushing
Compound Gates
Logical Effort Example
Input Ordering
Asymmetric Gates
Skewed Gates
Best P/N ratio
8: Combinational Circuits
CMOS VLSI Design
Slide 2
Example 1
module mux(input s, d0, d1,
output y);
assign y = s ? d1 : d0;
endmodule
1) Sketch a design using AND, OR, and NOT gates.
8: Combinational Circuits
CMOS VLSI Design
Slide 3
Example 1
module mux(input s, d0, d1,
output y);
assign y = s ? d1 : d0;
endmodule
1) Sketch a design using AND, OR, and NOT gates.
D0
S
Y
D1
S
8: Combinational Circuits
CMOS VLSI Design
Slide 4
Example 2
2) Sketch a design using NAND, NOR, and NOT gates.
Assume ~S is available.
8: Combinational Circuits
CMOS VLSI Design
Slide 5
Example 2
2) Sketch a design using NAND, NOR, and NOT gates.
Assume ~S is available.
D0
S
Y
D1
S
8: Combinational Circuits
CMOS VLSI Design
Slide 6
Bubble Pushing
Start with network of AND / OR gates
Convert to NAND / NOR + inverters
Push bubbles around to simplify logic
– Remember DeMorgan’s Law
Y
Y
(a)
(b)
Y
(c)
D
8: Combinational Circuits
Y
(d)
CMOS VLSI Design
Slide 7
Example 3
3) Sketch a design using one compound gate and one
NOT gate. Assume ~S is available.
8: Combinational Circuits
CMOS VLSI Design
Slide 8
Example 3
3) Sketch a design using one compound gate and one
NOT gate. Assume ~S is available.
D0
S
D1
S
8: Combinational Circuits
Y
CMOS VLSI Design
Slide 9
Compound Gates
Logical Effort of compound gates
unit inverter
AOI21
YA
Y A BC
Y A BC D
A
B
C
A
B
C
D
A
Y
A
A
2
1
Y
AOI22
Y
4 B
C
A
2
B
2
4
4
C
Y
1
Complex AOI
Y
A
4 B
4
C
4 D
4
A
2 C
2
B
2 D
2
Y
Y A B C D E
D
E
A
B
C
Y
B
6
C
6
A
3
D
6
E
6
E
2
A
2
D
2
2
C
gA = 3/3
gA = 6/3
gA =
gA =
p = 3/3
gB = 6/3
gB =
gB =
gC = 5/3
gC =
gC =
p = 7/3
gD =
gD =
p=
gE =
B
Y
2
p=
8: Combinational Circuits
CMOS VLSI Design
Slide 10
Compound Gates
Logical Effort of compound gates
unit inverter
AOI21
YA
Y A BC
Y A BC D
A
B
C
A
B
C
D
A
Y
A
A
2
1
Y
AOI22
Y
4 B
C
A
2
B
2
4
4
C
Y
1
Complex AOI
Y
A
4 B
4
C
4 D
4
A
2 C
2
B
2 D
2
Y
Y A B C D E
D
E
A
B
C
Y
B
6
C
6
A
3
D
6
E
6
E
2
A
2
D
2
2
C
B
gA = 3/3
gA = 6/3
gA = 6/3
gA = 5/3
p = 3/3
gB = 6/3
gB = 6/3
gB = 8/3
gC = 5/3
gC = 6/3
gC = 8/3
p = 7/3
gD = 6/3
gD = 8/3
p = 12/3
gE = 8/3
Y
2
p = 16/3
8: Combinational Circuits
CMOS VLSI Design
Slide 11
Example 4
The multiplexer has a maximum input capacitance of
16 units on each input. It must drive a load of 160
units. Estimate the delay of the NAND and
compound gate designs.
8: Combinational Circuits
CMOS VLSI Design
Slide 12
Example 4
The multiplexer has a maximum input capacitance of
16 units on each input. It must drive a load of 160
units. Estimate the delay of the NAND and
compound gate designs.
D0
S
Y
D1
S
D0
S
D1
S
Y
H = 160 / 16 = 10
B=1
N=2
8: Combinational Circuits
CMOS VLSI Design
Slide 13
NAND Solution
D0
S
Y
D1
S
8: Combinational Circuits
CMOS VLSI Design
Slide 14
NAND Solution
P 224
G ( 4 / 3) ( 4 / 3) 16 / 9
F G B H 160 / 9
fˆ
N
D0
S
Y
D1
S
F 4.2
D N fˆ P 12.4
8: Combinational Circuits
CMOS VLSI Design
Slide 15
Compound Solution
D0
S
D1
S
8: Combinational Circuits
CMOS VLSI Design
Y
Slide 16
Compound Solution
P 4 1 5
G (6 / 3) (1) 2
F G B H 20
fˆ
N
D0
S
D1
S
Y
F 4.5
D N fˆ P 14
8: Combinational Circuits
CMOS VLSI Design
Slide 17
Example 5
Annotate your designs with transistor sizes that
achieve this delay.
Y
8: Combinational Circuits
CMOS VLSI Design
Y
Slide 18
Example 5
Annotate your designs with transistor sizes that
achieve this delay.
8
8
8
8
25
25
25
8
8
Y
25
10
10
10
10
24
6
6
12
6
6
Y
8
8
16
8: Combinational Circuits
160 * (4/3) / 4.2 = 50
CMOS VLSI Design
16
160 * 1 / 4.5 = 36
Slide 19
Input Order
Our parasitic delay model was too simple
– Calculate parasitic delay for Y falling
• If A arrives latest?
• If B arrives latest?
2
2
A
2
B
2x
8: Combinational Circuits
Y
6C
2C
CMOS VLSI Design
Slide 20
Input Order
Our parasitic delay model was too simple
– Calculate parasitic delay for Y falling
• If A arrives latest? 2
• If B arrives latest? 2.33
2
2
A
2
B
2x
8: Combinational Circuits
Y
6C
2C
CMOS VLSI Design
Slide 21
Inner & Outer Inputs
Outer input is closest to rail (B)
Inner input is closest to output (A)
2
A
B
If input arrival time is known
– Connect latest input to inner terminal
8: Combinational Circuits
CMOS VLSI Design
2
Y
2
2
Slide 22
Asymmetric Gates
Asymmetric gates favor one input over another
Ex: suppose input A of a NAND gate is most critical
– Use smaller transistor on A (less capacitance)
A
– Boost size of noncritical input
reset
– So total resistance is same
gA =
2
Y
A
4/3
gB =
reset
gtotal = gA + gB =
Asymmetric gate approaches g = 1 on critical input
But total logical effort goes up
8: Combinational Circuits
CMOS VLSI Design
Y
Slide 23
Asymmetric Gates
Asymmetric gates favor one input over another
Ex: suppose input A of a NAND gate is most critical
– Use smaller transistor on A (less capacitance)
A
– Boost size of noncritical input
reset
– So total resistance is same
gA = 10/9
2
2
Y
A
4/3
gB = 2
4
reset
gtotal = gA + gB = 28/9
Asymmetric gate approaches g = 1 on critical input
But total logical effort goes up
8: Combinational Circuits
CMOS VLSI Design
Y
Slide 24
Symmetric Gates
Inputs can be made perfectly symmetric
2
2
A
1
1
B
1
1
8: Combinational Circuits
CMOS VLSI Design
Y
Slide 25
Skewed Gates
Skewed gates favor one edge over another
Ex: suppose rising output of inverter is most critical
– Downsize noncritical nMOS transistor
HI-skew
inverter
unskewed inverter
(equal rise resistance)
2
A
unskewed inverter
(equal fall resistance)
2
Y
1/2
A
1
Y
A
1
Y
1/2
Calculate logical effort by comparing to unskewed
inverter with same effective resistance on that edge.
– gu =
– gd =
8: Combinational Circuits
CMOS VLSI Design
Slide 26
Skewed Gates
Skewed gates favor one edge over another
Ex: suppose rising output of inverter is most critical
– Downsize noncritical nMOS transistor
HI-skew
inverter
unskewed inverter
(equal rise resistance)
2
A
unskewed inverter
(equal fall resistance)
2
Y
1/2
A
1
Y
A
1
Y
1/2
Calculate logical effort by comparing to unskewed
inverter with same effective resistance on that edge.
– gu = 2.5 / 3 = 5/6
– gd = 2.5 / 1.5 = 5/3
8: Combinational Circuits
CMOS VLSI Design
Slide 27
HI- and LO-Skew
Def: Logical effort of a skewed gate for a particular
transition is the ratio of the input capacitance of that
gate to the input capacitance of an unskewed
inverter delivering the same output current for the
same transition.
Skewed gates reduce size of noncritical transistors
– HI-skew gates favor rising output (small nMOS)
– LO-skew gates favor falling output (small pMOS)
Logical effort is smaller for favored direction
But larger for the other direction
8: Combinational Circuits
CMOS VLSI Design
Slide 28
Catalog of Skewed Gates
Inverter
NAND2
2
unskewed
1
2
Y
2
A
NOR2
Y
gu = 1
gd = 1
gavg = 1
A
2
B
2
B
4
A
4
Y
1
gu = 4/3
gd = 4/3
gavg = 4/3
1
gu = 5/3
gd = 5/3
gavg = 5/3
B
HI-skew
Y
2
A
1/2
Y
gu = 5/6
gd = 5/3
gavg = 5/4
A
A
Y
B
gu =
gd =
gavg =
gu =
gd =
gavg =
B
LO-skew
Y
1
A
1
Y
gu = 4/3
gd = 2/3
gavg = 1
8: Combinational Circuits
A
A
B
Y
gu =
gd =
gavg =
CMOS VLSI Design
gu =
gd =
gavg =
Slide 29
Catalog of Skewed Gates
Inverter
NAND2
2
unskewed
1
Y
gu = 1
gd = 1
gavg = 1
A
2
B
2
2
HI-skew
1/2
Y
gu = 5/6
gd = 5/3
gavg = 5/4
1
B
1
1
LO-skew
1
Y
gu = 4/3
gd = 2/3
gavg = 1
8: Combinational Circuits
2
B
2
4
1
1
B
4
A
4
1/2
gu =
gd =
gavg =
1
A
A
gu = 5/3
gd = 5/3
gavg = 5/3
Y
Y
1
A
4
gu = 4/3
gd = 4/3
gavg = 4/3
2
A
B
Y
Y
2
A
2
Y
2
A
NOR2
1/2
B
2
A
2
gu =
gd =
gavg =
Y
gu =
gd =
gavg =
CMOS VLSI Design
1
1
gu =
gd =
gavg =
Slide 30
Catalog of Skewed Gates
Inverter
NAND2
2
unskewed
1
Y
gu = 1
gd = 1
gavg = 1
A
2
B
2
2
HI-skew
1/2
Y
gu = 5/6
gd = 5/3
gavg = 5/4
1
B
1
1
LO-skew
1
Y
gu = 4/3
gd = 2/3
gavg = 1
8: Combinational Circuits
2
B
2
4
1
1
B
4
A
4
1/2
gu = 1
gd = 2
gavg = 3/2
1
A
A
gu = 5/3
gd = 5/3
gavg = 5/3
Y
Y
1
A
4
gu = 4/3
gd = 4/3
gavg = 4/3
2
A
B
Y
Y
2
A
2
Y
2
A
NOR2
1/2
B
2
A
2
gu = 3/2
gd = 3
gavg = 9/4
Y
gu = 2
gd = 1
gavg = 3/2
CMOS VLSI Design
1
1
gu = 2
gd = 1
gavg = 3/2
Slide 31
Asymmetric Skew
Combine asymmetric and skewed gates
– Downsize noncritical transistor on unimportant
input
– Reduces parasitic delay for critical input
A
reset
Y
1
A
reset
8: Combinational Circuits
2
Y
4/3
4
CMOS VLSI Design
Slide 32
Best P/N Ratio
We have selected P/N ratio for unit rise and fall
resistance (m = 2-3 for an inverter).
Alternative: choose ratio for least average delay
Ex: inverter
P
– Delay driving identical inverter
A
1
– tpdf =
– tpdr =
– tpd =
– Differentiate tpd w.r.t. P
– Least delay for P =
8: Combinational Circuits
CMOS VLSI Design
Slide 33
Best P/N Ratio
We have selected P/N ratio for unit rise and fall
resistance (m = 2-3 for an inverter).
Alternative: choose ratio for least average delay
Ex: inverter
P
– Delay driving identical inverter
A
1
– tpdf = (P+1)
– tpdr = (P+1)(m/P)
– tpd = (P+1)(1+m/P)/2 = (P + 1 + m + m/P)/2
– Differentiate tpd w.r.t. P
– Least delay for P = m
8: Combinational Circuits
CMOS VLSI Design
Slide 34
P/N Ratios
In general, best P/N ratio is sqrt of equal delay ratio.
– Only improves average delay slightly for inverters
– But significantly decreases area and power
Inverter
NAND2
2
fastest
P/N ratio
A
1.414
Y
1
gu =
gd =
gavg =
8: Combinational Circuits
NOR2
2
Y
A
2
B
2
B
2
A
2
Y
gu =
gd =
gavg =
CMOS VLSI Design
1
1
gu =
gd =
gavg =
Slide 35
P/N Ratios
In general, best P/N ratio is sqrt of that giving equal
delay.
– Only improves average delay slightly for inverters
– But significantly decreases area and power
Inverter
NAND2
2
fastest
P/N ratio
A
1.414
Y
1
gu = 1.15
gd = 0.81
gavg = 0.98
8: Combinational Circuits
NOR2
2
Y
A
2
B
2
B
2
A
2
Y
gu = 4/3
gd = 4/3
gavg = 4/3
CMOS VLSI Design
1
1
gu = 2
gd = 1
gavg = 3/2
Slide 36
Observations
For speed:
– NAND vs. NOR
– Many simple stages vs. fewer high fan-in stages
– Latest-arriving input
For area and power:
– Many simple stages vs. fewer high fan-in stages
8: Combinational Circuits
CMOS VLSI Design
Slide 37