VLSI Design EE 447/547
Download
Report
Transcript VLSI Design EE 447/547
EE 447/547 VLSI Design
Lecture 9:
Sequential Circuits
VLSI Design EE 447/547
Sequential circuits
1
Outline
Floorplanning
Sequencing
Sequencing Element Design
Max and Min-Delay
Clock Skew
Time Borrowing
Two-Phase Clocking
VLSI Design EE 447/547
Sequential circuits
2
Project Strategy
Proposal
Floorplan
Begins with block diagram
Annotate dimensions and location of each block
Requires detailed paper design
Schematic
Specifies inputs, outputs, relation between them
Make paper design simulate correctly
Layout
Physical design, DRC, NCC, ERC
VLSI Design EE 447/547
Sequential circuits
3
Floorplan
How do you estimate block areas?
Begin with block diagram
Each block has
Inputs
Outputs
Function (draw schematic)
Type: array, datapath, random logic
Estimation depends on type of logic
VLSI Design EE 447/547
Sequential circuits
4
MIPS Floorplan
10 I/O pads
mips
(4.6 M2)
control
1500 x 400
(0.6 M2)
zipper 2700 x 250
datapath
2700 x 1050
(2.8 M2)
10 I/O pads
1690
3500
5000
10 I/O pads
wiring channel: 30 tracks = 240
alucontrol
200 x 100
(20 k2)
bitslice 2700 x 100
2700
3500
10 I/O pads
5000
VLSI Design EE 447/547
Sequential circuits
5
Area Estimation
Arrays:
Datapaths
Layout basic cell
Calculate core area from # of cells
Allow area for decoders, column circuitry
Sketch slice plan
Count area of cells from cell library
Ensure wiring is possible
Random logic
Compare complexity do a design you have done
VLSI Design EE 447/547
Sequential circuits
6
MIPS Slice Plan
srcB
writedata
memdata
adr
bitlines
srcA
aluresult
immediate
pc
aluout
44 24 93 93 93 93 93 44 24 52 48 48 48 48 16 86 93 131 93 44 24 93 131 39 93 39 24 44 39 39 160131
mux4
fulladder
or2
and2
mux2
inv
and2
zerodetect
PC
flop
and2
Sequential circuits
mux4
VLSI Design EE 447/547
aluout
srcA
flop
inv
mux2
srcB
flop
mux4
flop
readmux
writemux
MDR
adrmux
register file
ramslice
srampullup
dualsrambit0
dualsram
dualsram
dualsram
writedriver
inv
mux2
flop
flop
flop
flop
flop
inv
mux2
IR3...0
ALU
7
Typical Layout Densities
Typical numbers of high-quality layout
Derate by 2 for class projects to allow routing and some
sloppy layout.
Allocate space for big wiring channels
Element
Area
Random logic (2 metal layers)
1000-1500 2 / transistor
Datapath
250 – 750 2 / transistor
Or 6 WL + 360 2 / transistor
SRAM
1000 2 / bit
DRAM
100 2 / bit
ROM
100 2 / bit
VLSI Design EE 447/547
Sequential circuits
8
Sequencing
Combinational logic
output depends on current inputs
Sequential logic
output depends on current and previous inputs
Requires separating previous, current, future
Called state or tokens
Ex: FSM, pipeline
clk
in
clk
clk
clk
out
CL
CL
Finite State Machine
CL
Pipeline
VLSI Design EE 447/547
Sequential circuits
9
Sequencing Cont.
If tokens moved through pipeline at constant
speed, no sequencing elements would be
necessary
Ex: fiber-optic cable
Light pulses (tokens) are sent down cable
Next pulse sent before first reaches end of cable
No need for hardware to separate pulses
But dispersion sets min time between pulses
This is called wave pipelining in circuits
In most circuits, dispersion is high
Delay fast tokens so they don’t catch slow ones.
VLSI Design EE 447/547
Sequential circuits
10
Sequencing Overhead
Use flip-flops to delay fast tokens so they
move through exactly one stage each cycle.
Inevitably adds some delay to the slow
tokens
Makes circuit slower than just the logic delay
Called sequencing overhead
Some people call this clocking overhead
But it applies to asynchronous circuits too
Inevitable side effect of maintaining sequence
VLSI Design EE 447/547
Sequential circuits
11
Sequencing Elements
Latch: Level sensitive
Flip-flop: edge triggered
A.k.a. master-slave flip-flop, D flip-flop, D register
clk
Timing Diagrams
Transparent
Opaque
Edge-trigger
D
clk
Q
D
Flop
a.k.a. transparent latch, D latch
Latch
Q
clk
D
Q (latch)
Q (flop)
VLSI Design EE 447/547
Sequential circuits
12
Sequencing Elements
Latch: Level sensitive
Flip-flop: edge triggered
A.k.a. master-slave flip-flop, D flip-flop, D register
clk
Timing Diagrams
Transparent
Opaque
Edge-trigger
D
clk
Q
D
Flop
a.k.a. transparent latch, D latch
Latch
Q
clk
D
Q (latch)
Q (flop)
VLSI Design EE 447/547
Sequential circuits
13
Latch Design
Pass Transistor Latch
Pros
+
+
D
Q
Cons
VLSI Design EE 447/547
Sequential circuits
14
Latch Design
Pass Transistor Latch
Pros
+ Tiny
+ Low clock load
D
Cons
Q
Used in 1970’s
Vt drop
nonrestoring
backdriving
output noise sensitivity
dynamic
diffusion input
VLSI Design EE 447/547
Sequential circuits
15
Latch Design
Transmission gate
+
-
D
Q
VLSI Design EE 447/547
Sequential circuits
16
Latch Design
Transmission gate
+ No Vt drop
- Requires inverted clock
D
Q
VLSI Design EE 447/547
Sequential circuits
17
Latch Design
Inverting buffer
+
+
+ Fixes either
X
D
Q
D
Q
VLSI Design EE 447/547
Sequential circuits
18
Latch Design
Inverting buffer
+ Restoring
+ No backdriving
+ Fixes either
Output noise sensitivity
Or diffusion input
Inverted output
VLSI Design EE 447/547
Sequential circuits
X
D
Q
D
Q
19
Latch Design
Tristate feedback
+
X
D
Q
VLSI Design EE 447/547
Sequential circuits
20
Latch Design
Tristate feedback
+
Static
Backdriving risk
X
D
Static latches are now essential
VLSI Design EE 447/547
Sequential circuits
Q
21
Latch Design
Buffered input
+
+
X
D
Q
VLSI Design EE 447/547
Sequential circuits
22
Latch Design
Buffered input
+ Fixes diffusion input
+ Noninverting
X
D
Q
VLSI Design EE 447/547
Sequential circuits
23
Latch Design
Buffered output
+
Q
X
D
VLSI Design EE 447/547
Sequential circuits
24
Latch Design
Buffered output
+ No backdriving
X
D
Widely used in standard cells
Q
+ Very robust (most important)
Rather large
Rather slow (1.5 – 2 FO4 delays)
High clock loading
VLSI Design EE 447/547
Sequential circuits
25
Latch Design
Datapath latch
+
-
Q
X
D
VLSI Design EE 447/547
Sequential circuits
26
Latch Design
Datapath latch
+ Smaller, faster
- unbuffered input
Q
X
D
VLSI Design EE 447/547
Sequential circuits
27
Flip-Flop Design
Flip-flop is built as pair of back-to-back
latches
X
D
Q
Q
X
D
Q
VLSI Design EE 447/547
Sequential circuits
28
Enable
Enable: ignore clock when en = 0
Symbol
Multiplexer Design
Clock Gating Design
en
D
1
Latch
Q
0
en
Q
D
en
D
Q
en
D
1
0
Q
Q
D
en
Flop
D
Latch
Flop
Mux: increase latch D-Q delay
Clock Gating: increase en setup time, skew
Latch
Flop
Q
en
VLSI Design EE 447/547
Sequential circuits
29
Reset
Symbol
D
Q
D
reset
Synchronous Reset
Q
reset
D
Q
reset
reset
D
Flop
Force output low when reset asserted
Synchronous vs. asynchronous
Latch
Q
Q
Asynchronous Reset
Q
Q
reset
reset
D
D
reset
reset
VLSI Design EE 447/547
Sequential circuits
30
Set / Reset
Set forces output high when enabled
Flip-flop with asynchronous set and reset
reset
set
D
Q
set
reset
VLSI Design EE 447/547
Sequential circuits
31
Sequencing Methods
Tc
Flop
clk
Flop
clk
Combinational Logic
1
tnonoverlap
Combinational
Logic
Half-Cycle 1
1
Combinational
Logic
Latch
2
Latch
1
Half-Cycle 1
tpw
p
VLSI Design EE 447/547
Sequential circuits
p
Combinational Logic
Latch
Pulsed Latches
p
tnonoverlap
Tc/2
2
Latch
2-Phase Transparent Latches
clk
Latch
Flip-flops
2-Phase Latches
Pulsed Latches
Flip-Flops
32
Timing Diagrams
Contamination and
Propagation Delays
tcd
Logic Cont. Delay
tpcq
Latch/Flop Clk-Q Prop
Delay
tccq
Latch/Flop Clk-Q Cont.
Delay
tpdq
Latch D-Q Prop Delay
tpcq
Latch D-Q Cont. Delay
tsetup
Latch/Flop Setup Time
thold
Latch/Flop Hold Time
A
Combinational
Logic
A
tpd
Y
Y
clk
clk
Flop
Logic Prop. Delay
D
Q
tcd
tsetup
thold
D
tpcq
Q
D
tccq
clk
clk
Latch
tpd
tccq
Q
tsetup
tpcq
D
tcdq
thold
tpdq
Q
VLSI Design EE 447/547
Sequential circuits
33
Max-Delay: Flip-Flops
clk
sequencing overhead
clk
Q1
Combinational Logic
D2
F2
F1
t pd T c
Tc
clk
tsetup
tpcq
Q1
tpd
D2
VLSI Design EE 447/547
Sequential circuits
34
Max-Delay: Flip-Flops
sequencing overhead
clk
Q1
Combinational Logic
D2
F2
clk
F1
t pd T c t setup t pcq
Tc
clk
tsetup
tpcq
Q1
tpd
D2
VLSI Design EE 447/547
Sequential circuits
35
Max Delay: 2-Phase Latches
sequencing overhead
Q1
Combinational
Logic 1
D2
1
Q2
Combinational
Logic 2
D3
L3
D1
2
L2
L1
t pd t pd 1 t pd 2 T c
1
Q3
1
2
Tc
D1
tpdq1
Q1
tpd1
D2
tpdq2
Q2
tpd2
D3
VLSI Design EE 447/547
Sequential circuits
36
Max Delay: 2-Phase Latches
D1
sequencing overhead
Q1
Combinational
Logic 1
D2
1
Q2
Combinational
Logic 2
D3
L3
pdq
2
L2
2t
L1
t pd t pd 1 t pd 2 T c
1
Q3
1
2
Tc
D1
tpdq1
Q1
tpd1
D2
tpdq2
Q2
tpd2
D3
VLSI Design EE 447/547
Sequential circuits
37
Max Delay: Pulsed Latches
p
D1
sequencing overhead
p
Q1
D2
Combinational Logic
L2
L1
t pd T c m ax
Q2
Tc
D1
(a) tpw > tsetup
tpdq
Q1
tpd
D2
p
tpcq
Q1
Tc
tpd
tpw
tsetup
(b) tpw < tsetup
D2
VLSI Design EE 447/547
Sequential circuits
38
Max Delay: Pulsed Latches
D1
p
Q1
D2
Combinational Logic
L2
p
L1
t pd T c m ax t pdq , t pcq t setup t pw
Q2
sequencing overhead
Tc
D1
(a) tpw > tsetup
tpdq
Q1
tpd
D2
p
tpcq
Q1
Tc
tpd
tpw
tsetup
(b) tpw < tsetup
D2
VLSI Design EE 447/547
Sequential circuits
39
Min-Delay: Flip-Flops
clk
F1
t cd
Q1
CL
clk
F2
D2
clk
Q1 tccq
D2
tcd
thold
VLSI Design EE 447/547
Sequential circuits
40
Min-Delay: Flip-Flops
clk
F1
t cd t hold t ccq
Q1
CL
clk
F2
D2
clk
Q1 tccq
D2
tcd
thold
VLSI Design EE 447/547
Sequential circuits
41
Min-Delay: 2-Phase Latches
1
L1
t cd 1, t cd 2
Q1
CL
Hold time reduced by
nonoverlap
D2
Paradox: hold applies
twice each cycle, vs.
only once for flops.
1
L2
2
tnonoverlap
tccq
2
Q1
D2
But a flop is made of
two latches!
tcd
thold
VLSI Design EE 447/547
Sequential circuits
42
Min-Delay: 2-Phase Latches
1
L1
t cd 1, t cd 2 t hold t ccq t nonoverlap
Q1
CL
Hold time reduced by
nonoverlap
D2
Paradox: hold applies
twice each cycle, vs.
only once for flops.
1
L2
2
tnonoverlap
tccq
2
Q1
D2
But a flop is made of
two latches!
tcd
thold
VLSI Design EE 447/547
Sequential circuits
43
Min-Delay: Pulsed Latches
p
Q1
CL
p
D2
p
L2
Hold time increased
by pulse width
L1
t cd
tpw
thold
Q1 tccq
tcd
D2
VLSI Design EE 447/547
Sequential circuits
44
Min-Delay: Pulsed Latches
p
Q1
CL
p
D2
p
L2
Hold time increased
by pulse width
L1
t cd t hold t ccq t pw
tpw
thold
Q1 tccq
tcd
D2
VLSI Design EE 447/547
Sequential circuits
45
Time Borrowing
In a flop-based system:
Data launches on one rising edge
Must setup before next rising edge
If it arrives late, system fails
If it arrives early, time is wasted
Flops have hard edges
In a latch-based system
Data can pass through latch while transparent
Long cycle of logic can borrow time into next
As long as each loop completes in one cycle
VLSI Design EE 447/547
Sequential circuits
46
Time Borrowing Example
1
2
Combinational Logic
Borrowing time across
half-cycle boundary
Combinational
Logic
Borrowing time across
pipeline stage boundary
2
Combinational Logic
Latch
(b)
Latch
1
1
Latch
2
Latch
(a)
Latch
1
Combinational
Logic
Loops may borrow time internally but must complete within the cycle
VLSI Design EE 447/547
Sequential circuits
47
How Much Borrowing?
2
t setup t nonoverlap
D1
L1
t borrow
Tc
1
2
Q1
Combinational Logic 1
D2
L2
2-Phase Latches
Q2
1
Pulsed Latches
2
tnonoverlap
Tc
t borrow t pw t setup
Tc/2
Nominal Half-Cycle 1 Delay
tborrow
tsetup
D2
VLSI Design EE 447/547
Sequential circuits
48
Clock Skew
We have assumed zero clock skew
Clocks really have uncertainty in arrival time
Decreases maximum propagation delay
Increases minimum contamination delay
Decreases time borrowing
VLSI Design EE 447/547
Sequential circuits
49
Skew: Flip-Flops
Combinational Logic
D2
Tc
clk
tpcq
t cd t hold t ccq t skew
Q1
tskew
tpdq
tsetup
D2
F1
clk
Q1
CL
clk
D2
F2
sequencing overhead
Q1
F1
t pd T c t pcq t setup t skew
clk
F2
clk
tskew
clk
thold
Q1 tccq
D2
tcd
VLSI Design EE 447/547
Sequential circuits
50
Skew: Latches
2t
2
c
D2
Q2
Combinational
Logic 2
D3
Q3
2
t setup t nonoverlap t skew
Pulsed Latches
t T m ax t , t
pd
Combinational
Logic 1
1
t cd 1 , t cd 2 t hold t ccq t nonoverlap t skew
Tc
Q1
1
pdq
sequencing overhead
t borrow
2
L3
D1
L1
t pd T c
1
L2
2-Phase Latches
pdq
pcq
t setup t pw t skew
sequencing overhead
t cd t hold t pw t ccq t skew
t borrow t pw t setup t skew
VLSI Design EE 447/547
Sequential circuits
51
Two-Phase Clocking
If setup times are violated, reduce clock speed
If hold times are violated, chip fails at any speed
In this class, working chips are most important
No tools to analyze clock skew
An easy way to guarantee hold times is to use 2phase latches with big nonoverlap times
Call these clocks 1, 2 (ph1, ph2)
VLSI Design EE 447/547
Sequential circuits
52
Safe Flip-Flop
In class, use flip-flop with nonoverlapping
clocks
Very slow – nonoverlap adds to setup time
But no hold times
In industry, use a better timing analyzer
Add buffers to slow signals if hold time is at risk
Q
X
D
Q
VLSI Design EE 447/547
Sequential circuits
53
Summary
Flip-Flops:
2-Phase Transparent Latches:
Very easy to use, supported by all tools
Lots of skew tolerance and time borrowing
Pulsed Latches:
Fast, some skew tol & borrow, hold time risk
VLSI Design EE 447/547
Sequential circuits
54