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Introduction to CMOS VLSI Design Lecture 10: Sequential Circuits David Harris Harvey Mudd College Spring 2004 Outline Floorplanning Sequencing Sequencing Element Design Max and Min-Delay Clock Skew Time Borrowing Two-Phase Clocking 10: Sequential Circuits CMOS VLSI Design Slide 2 Project Strategy Proposal – Specifies inputs, outputs, relation between them Floorplan – Begins with block diagram – Annotate dimensions and location of each block – Requires detailed paper design Schematic – Make paper design simulate correctly Layout – Physical design, DRC, NCC, ERC 10: Sequential Circuits CMOS VLSI Design Slide 3 Floorplan How do you estimate block areas? – Begin with block diagram – Each block has • Inputs • Outputs • Function (draw schematic) • Type: array, datapath, random logic Estimation depends on type of logic 10: Sequential Circuits CMOS VLSI Design Slide 4 MIPS Floorplan 10 I/O pads mips (4.6 M2) control 1500 x 400 (0.6 M2) zipper 2700 x 250 datapath 2700 x 1050 (2.8 M2) 10 I/O pads 1690 3500 5000 10 I/O pads wiring channel: 30 tracks = 240 alucontrol 200 x 100 (20 k2) bitslice 2700 x 100 2700 3500 10 I/O pads 5000 10: Sequential Circuits CMOS VLSI Design Slide 5 Area Estimation Arrays: – Layout basic cell – Calculate core area from # of cells – Allow area for decoders, column circuitry Datapaths – Sketch slice plan – Count area of cells from cell library – Ensure wiring is possible Random logic – Compare complexity do a design you have done 10: Sequential Circuits CMOS VLSI Design Slide 6 MIPS Slice Plan srcB writedata memdata adr bitlines srcA aluresult immediate pc aluout 44 24 93 93 93 93 93 44 24 52 48 48 48 48 16 86 93 131 93 44 24 93 131 39 93 39 24 44 39 39 160131 mux4 fulladder or2 and2 mux2 inv and2 zerodetect aluout PC flop and2 mux4 flop CMOS VLSI Design srcA inv srcB mux2 flop mux4 flop readmux writemux MDR register file ramslice srampullup dualsrambit0 dualsram dualsram dualsram writedriver inv mux2 flop adrmux 10: Sequential Circuits flop flop flop flop inv mux2 IR3...0 ALU Slide 7 Typical Layout Densities Typical numbers of high-quality layout Derate by 2 for class projects to allow routing and some sloppy layout. Allocate space for big wiring channels Element Area Random logic (2 metal layers) 1000-1500 2 / transistor Datapath 250 – 750 2 / transistor Or 6 WL + 360 2 / transistor SRAM 1000 2 / bit DRAM 100 2 / bit ROM 100 2 / bit 10: Sequential Circuits CMOS VLSI Design Slide 8 Sequencing Combinational logic – output depends on current inputs Sequential logic – output depends on current and previous inputs – Requires separating previous, current, future – Called state or tokens – Ex: FSM, pipeline clk in clk clk clk out CL CL Finite State Machine 10: Sequential Circuits CL Pipeline CMOS VLSI Design Slide 9 Sequencing Cont. If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiber-optic cable – Light pulses (tokens) are sent down cable – Next pulse sent before first reaches end of cable – No need for hardware to separate pulses – But dispersion sets min time between pulses This is called wave pipelining in circuits In most circuits, dispersion is high – Delay fast tokens so they don’t catch slow ones. 10: Sequential Circuits CMOS VLSI Design Slide 10 Sequencing Overhead Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay – Called sequencing overhead Some people call this clocking overhead – But it applies to asynchronous circuits too – Inevitable side effect of maintaining sequence 10: Sequential Circuits CMOS VLSI Design Slide 11 Sequencing Elements Latch: Level sensitive – a.k.a. transparent latch, D latch Flip-flop: edge triggered – A.k.a. master-slave flip-flop, D flip-flop, D register Timing Diagrams – Transparent – Opaque – Edge-trigger clk Q D Flop D Latch clk Q clk D Q (latch) Q (flop) 10: Sequential Circuits CMOS VLSI Design Slide 12 Sequencing Elements Latch: Level sensitive – a.k.a. transparent latch, D latch Flip-flop: edge triggered – A.k.a. master-slave flip-flop, D flip-flop, D register Timing Diagrams – Transparent – Opaque – Edge-trigger clk Q D Flop D Latch clk Q clk D Q (latch) Q (flop) 10: Sequential Circuits CMOS VLSI Design Slide 13 Latch Design Pass Transistor Latch Pros + + Cons – – – – – – 10: Sequential Circuits CMOS VLSI Design D Q Slide 14 Latch Design Pass Transistor Latch Pros + Tiny + Low clock load Cons – Vt drop – nonrestoring – backdriving – output noise sensitivity – dynamic – diffusion input 10: Sequential Circuits CMOS VLSI Design D Q Used in 1970’s Slide 15 Latch Design Transmission gate + - D Q 10: Sequential Circuits CMOS VLSI Design Slide 16 Latch Design Transmission gate + No Vt drop - Requires inverted clock D Q 10: Sequential Circuits CMOS VLSI Design Slide 17 Latch Design Inverting buffer + + + Fixes either • • – 10: Sequential Circuits X D Q D Q CMOS VLSI Design Slide 18 Latch Design Inverting buffer + Restoring + No backdriving + Fixes either • Output noise sensitivity • Or diffusion input – Inverted output 10: Sequential Circuits CMOS VLSI Design X D Q D Q Slide 19 Latch Design Tristate feedback + – X D Q 10: Sequential Circuits CMOS VLSI Design Slide 20 Latch Design Tristate feedback + Static – Backdriving risk X D Q Static latches are now essential 10: Sequential Circuits CMOS VLSI Design Slide 21 Latch Design Buffered input + + X D Q 10: Sequential Circuits CMOS VLSI Design Slide 22 Latch Design Buffered input + Fixes diffusion input + Noninverting X D Q 10: Sequential Circuits CMOS VLSI Design Slide 23 Latch Design Buffered output + Q X D 10: Sequential Circuits CMOS VLSI Design Slide 24 Latch Design Buffered output + No backdriving X D Widely used in standard cells + Very robust (most important) - Rather large - Rather slow (1.5 – 2 FO4 delays) - High clock loading 10: Sequential Circuits CMOS VLSI Design Q Slide 25 Latch Design Datapath latch + - Q X D 10: Sequential Circuits CMOS VLSI Design Slide 26 Latch Design Datapath latch + Smaller, faster - unbuffered input Q X D 10: Sequential Circuits CMOS VLSI Design Slide 27 Flip-Flop Design Flip-flop is built as pair of back-to-back latches X D Q X D Q 10: Sequential Circuits Q CMOS VLSI Design Slide 28 Enable Enable: ignore clock when en = 0 – Mux: increase latch D-Q delay – Clock Gating: increase en setup time, skew Symbol Multiplexer Design Clock Gating Design en D 1 Q 0 en Q D en 1 0 Q Q D en Flop D Flop Flop Q en D Latch Latch D Latch Q en 10: Sequential Circuits CMOS VLSI Design Slide 29 Reset Force output low when reset asserted Synchronous vs. asynchronous Q D reset Synchronous Reset Q reset D Q Q Asynchronous Reset Q Q reset reset D D reset reset 10: Sequential Circuits Q reset reset D Flop Symbol D Latch CMOS VLSI Design Slide 30 Set / Reset Set forces output high when enabled Flip-flop with asynchronous set and reset reset set D Q set reset 10: Sequential Circuits CMOS VLSI Design Slide 31 Sequencing Methods clk clk Combinational Logic tnonoverlap Combinational Logic 1 Combinational Logic Latch 2 Latch 1 Half-Cycle 1 tpw CMOS VLSI Design p Combinational Logic Latch p Latch Pulsed Latches p tnonoverlap Tc/2 2 Latch 2-Phase Transparent Latches 1 Half-Cycle 1 10: Sequential Circuits Flop clk Flop Flip-Flops Flip-flops 2-Phase Latches Pulsed Latches Tc Slide 32 Timing Diagrams Contamination and Propagation Delays A A tpd Logic Prop. Delay tcd Logic Cont. Delay tpcq Latch/Flop Clk-Q Prop Delay tccq Latch/Flop Clk-Q Cont. Delay tpdq Latch D-Q Prop Delay tpcq Latch D-Q Cont. Delay tsetup Latch/Flop Setup Time thold Combinational Logic Y Y clk Flop clk D Q tcd tsetup thold D tpcq Q Latch D tccq clk clk tccq Q Latch/Flop Hold Time 10: Sequential Circuits tpd tsetup tpcq D tcdq thold tpdq Q CMOS VLSI Design Slide 33 Max-Delay: Flip-Flops clk sequencing overhead clk Q1 Combinational Logic D2 F2 F1 t pd Tc Tc clk tsetup tpcq Q1 tpd D2 10: Sequential Circuits CMOS VLSI Design Slide 34 clk sequencing overhead clk Q1 Combinational Logic D2 F2 t pd Tc tsetup t pcq F1 Max-Delay: Flip-Flops Tc clk tsetup tpcq Q1 tpd D2 10: Sequential Circuits CMOS VLSI Design Slide 35 Max Delay: 2-Phase Latches Q1 Combinational Logic 1 D2 1 Q2 Combinational Logic 2 D3 L3 D1 sequencing overhead 2 L2 L1 t pd t pd 1 t pd 2 Tc 1 Q3 1 2 Tc D1 Q1 tpdq1 tpd1 D2 tpdq2 Q2 tpd2 D3 10: Sequential Circuits CMOS VLSI Design Slide 36 Max Delay: 2-Phase Latches D1 sequencing overhead Q1 Combinational Logic 1 D2 1 Q2 Combinational Logic 2 D3 L3 pdq 2 L2 2t L1 t pd t pd 1 t pd 2 Tc 1 Q3 1 2 Tc D1 Q1 tpdq1 tpd1 D2 tpdq2 Q2 tpd2 D3 10: Sequential Circuits CMOS VLSI Design Slide 37 Max Delay: Pulsed Latches p D1 sequencing overhead p Q1 D2 Combinational Logic L2 L1 t pd Tc max Q2 Tc D1 (a) tpw > tsetup tpdq Q1 tpd D2 p tpcq Q1 Tc tpd tpw tsetup (b) tpw < tsetup D2 10: Sequential Circuits CMOS VLSI Design Slide 38 Max Delay: Pulsed Latches D1 sequencing overhead p Q1 D2 Combinational Logic L2 p L1 t pd Tc max t pdq , t pcq tsetup t pw Q2 Tc D1 (a) tpw > tsetup tpdq Q1 tpd D2 p tpcq Q1 Tc tpd tpw tsetup (b) tpw < tsetup D2 10: Sequential Circuits CMOS VLSI Design Slide 39 Min-Delay: Flip-Flops clk F1 tcd Q1 CL clk F2 D2 clk Q1 tccq D2 10: Sequential Circuits tcd thold CMOS VLSI Design Slide 40 Min-Delay: Flip-Flops clk F1 tcd thold tccq Q1 CL clk F2 D2 clk Q1 tccq D2 10: Sequential Circuits tcd thold CMOS VLSI Design Slide 41 Min-Delay: 2-Phase Latches 1 L1 tcd1,tcd 2 1 L2 D2 Paradox: hold applies twice each cycle, vs. only once for flops. tnonoverlap tccq 2 Q1 D2 10: Sequential Circuits CL 2 Hold time reduced by nonoverlap But a flop is made of two latches! Q1 tcd thold CMOS VLSI Design Slide 42 Min-Delay: 2-Phase Latches 1 L1 tcd1,tcd 2 thold tccq tnonoverlap 1 L2 D2 Paradox: hold applies twice each cycle, vs. only once for flops. tnonoverlap tccq 2 Q1 D2 10: Sequential Circuits CL 2 Hold time reduced by nonoverlap But a flop is made of two latches! Q1 tcd thold CMOS VLSI Design Slide 43 Min-Delay: Pulsed Latches p Q1 CL p D2 p L2 Hold time increased by pulse width L1 tcd tpw thold Q1 tccq tcd D2 10: Sequential Circuits CMOS VLSI Design Slide 44 Min-Delay: Pulsed Latches p Q1 CL p D2 p L2 Hold time increased by pulse width L1 tcd thold tccq t pw tpw thold Q1 tccq tcd D2 10: Sequential Circuits CMOS VLSI Design Slide 45 Time Borrowing In a flop-based system: – Data launches on one rising edge – Must setup before next rising edge – If it arrives late, system fails – If it arrives early, time is wasted – Flops have hard edges In a latch-based system – Data can pass through latch while transparent – Long cycle of logic can borrow time into next – As long as each loop completes in one cycle 10: Sequential Circuits CMOS VLSI Design Slide 46 Time Borrowing Example 1 2 Combinational Logic Borrowing time across half-cycle boundary Combinational Logic Borrowing time across pipeline stage boundary 2 Combinational Logic Latch (b) Latch 1 1 Latch 2 Latch (a) Latch 1 Combinational Logic Loops may borrow time internally but must complete within the cycle 10: Sequential Circuits CMOS VLSI Design Slide 47 How Much Borrowing? D1 L1 tborrow T c tsetup tnonoverlap 2 1 2 Q1 Combinational Logic 1 D2 L2 2-Phase Latches Q2 1 Pulsed Latches 2 tborrow t pw tsetup tnonoverlap Tc Tc/2 Nominal Half-Cycle 1 Delay tborrow tsetup D2 10: Sequential Circuits CMOS VLSI Design Slide 48 Clock Skew We have assumed zero clock skew Clocks really have uncertainty in arrival time – Decreases maximum propagation delay – Increases minimum contamination delay – Decreases time borrowing 10: Sequential Circuits CMOS VLSI Design Slide 49 Skew: Flip-Flops sequencing overhead Q1 F1 t pd Tc t pcq tsetup tskew clk Combinational Logic D2 F2 clk Tc clk tcd thold tccq tskew tpcq Q1 tskew tpdq tsetup D2 F1 clk Q1 CL D2 F2 clk tskew clk thold Q1 tccq D2 10: Sequential Circuits tcd CMOS VLSI Design Slide 50 Skew: Latches Q1 Combinational Logic 1 D2 1 Q2 Combinational Logic 2 D3 Q3 pdq 1 sequencing overhead tcd 1 , tcd 2 thold tccq tnonoverlap tskew tborrow 2 L3 2t D1 L1 t pd Tc 1 L2 2-Phase Latches 2 Tc tsetup tnonoverlap tskew 2 Pulsed Latches t pd Tc max t pdq , t pcq tsetup t pw tskew sequencing overhead tcd thold t pw tccq tskew tborrow t pw tsetup tskew 10: Sequential Circuits CMOS VLSI Design Slide 51 Two-Phase Clocking If setup times are violated, reduce clock speed If hold times are violated, chip fails at any speed In this class, working chips are most important – No tools to analyze clock skew An easy way to guarantee hold times is to use 2phase latches with big nonoverlap times Call these clocks 1, 2 (ph1, ph2) 10: Sequential Circuits CMOS VLSI Design Slide 52 Safe Flip-Flop In class, use flip-flop with nonoverlapping clocks – Very slow – nonoverlap adds to setup time – But no hold times In industry, use a better timing analyzer – Add buffers to slow signals if hold time is at risk X D Q 10: Sequential Circuits Q CMOS VLSI Design Slide 53 Summary Flip-Flops: – Very easy to use, supported by all tools 2-Phase Transparent Latches: – Lots of skew tolerance and time borrowing Pulsed Latches: – Fast, some skew tol & borrow, hold time risk 10: Sequential Circuits CMOS VLSI Design Slide 54