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EE5900 Advanced
Algorithms for
Robust VLSI CAD
Dr. Shiyan Hu
Office: EERC 731
The Wires
Adapted and modified from Digital Integrated Circuits: A Design Perspective
by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.
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Modern Interconnect
receivers
transmitters
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Modern Interconnect - II
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Interconnect Delay Dominates
Delay (psec)
300
250
Interconnect delay
200
150
100
Transistor/Gate delay
50
0
0.8
0.5
0.35 0.25
Technology generation (m)
Source: Gordon Moore, Chairman Emeritus, Intel Corp.
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Wire Model
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Capacitor
A
capacitor is a device that can store an
electric charge by applying a voltage
 The capacitance is measured by the
ratio of the charge stored to the applied
voltage
 Capacitance is measured in Farads
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3D Parasitic Capacitance

Given a set of conductors, compute the
capacitance between all pairs of conductors.
-
+
+
+
-
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1V
+
+
-
- -
C=Q/V
-
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Simplified Model
Area capacitance
(Parallel plate): area
overlap between
adjacent layers/substrate
 Fringing/coupling
capacitance:

 between side-walls on the
same layer
 between side-wall and
adjacent layers/substrate
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m3
m2
m2
m2
m1
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The Parallel Plate Model (Area Capacitance)
cint 
 di
t di
Current flow
WL
L
Electrical-field lines
W
H
tdi
Dielectric
Substrate
Capacitance is proportional to the overlap between the
conductors and inversely proportional to their separation
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Wire Capacitance
 More
difficult due to multiple layers,
different dielectric
=8.0
multiple
dielectric
m3
=4.0
m2 =3.9 m2 m2
=4.1
m1
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Simple Estimation Methods - I
C
= Ca*(overlap area)
+Cc*(length of parallel run)
+Cf*(perimeter)
 Coefficients Ca, Cc and Cf are given by
the fab
 Cadence Dracula
 Fast but inaccurate
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Simple Estimation Methods - II
 Consider
interaction between layer i
and layers i+1, i+2, i–1 and i–2
 Consider distance between
conductors on the same layer
 Cadence Silicon Ensemble
 Accuracy 50%
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Library Based Methods
 Build
a library of tens of thousands of
patterns and compute capacitance for
each pattern
 Partition layout into blocks, and match
with the library
 Accuracy 20%
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Accurate Methods In Industry
 Finite
difference/finite element method
 Most accurate, slowest
 Raphael
 Boundary
element method
 FastCap, Hicap
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Fringing versus Parallel Plate
Fringing/Coupli
ng capacitance
dominates.
(from [Bakoglu89])
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Wire Resistance

Basic formula R=(/h)(l/w)
l
h
w
  : resistivity
 h: thickness, fixed for a given technology and layer
number
 l: conductor length
 w: conductor width
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Typical Rs (Ohm/sq)
Min
Typical
Max
M1, M2
0.05
0.07
0.1
M3, M4
0.03
0.04
0.05
Poly
15
20
30
Diffusion 10
25
100
N-well
2000
5000
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1000
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Contact and Via

Contact:
 link metal with diffusion (active)
 Link metal with gate poly

Via:
 Link wire with wire
Overlapping two layers (diffusion, gate poly or
metal) and providing a contact hole filled with
metal
 Substrate Contact and Well Contact:

 Link substrate or well to supply voltage
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Interconnect
Delay
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Analysis of Simple RC Circuit
i(t)
R
R  i (t )  v (t )  vT (t )
vT(t) ±
C
d (Cv (t ))
dv(t )
i (t ) 
C
dt
dt
dv(t )
 RC
 v (t )  vT (t )
dt
state
variable
Input
waveform
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v(t)
Analysis of Simple RC Circuit
Step-input response:
v0
v0u(t)
v0(1-e-t/RC)u(t)
dv (t )
 v(t )  v0u (t )
dt
t
v(t )  Ke RC  v0u (t )
RC
match initial state:
v(0)  0
 K  v0u(t )  0  K  v0  0
output response for step-input:
v(t )  v0 (1  e
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t
RC
)u (t )
Wires
0.69RC

v(t) = v0(1 - e-t/RC) -- waveform
under step input v0u(t)

v(t)=0.5v0  t = 0.69RC
 i.e., delay = 0.69RC
(50% delay)
v(t)=0.1v0  t = 0.1RC
v(t)=0.9v0  t = 2.3RC
 i.e., rise time = 2.2RC (if defined as time from 10% to 90% of Vdd)


For simplicity, industry uses
TD = RC
(= Elmore delay)
We use both RC and 0.69RC in this course.
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Elmore Delay
Delay
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1. 50%-50%
point delay
2. Delay=RC
(Precisely,
0.69RC)
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Elmore Delay - III
What is the
delay of a wire?
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Elmore Delay – IV
Assume: Wire modeled by N equal-length segments
For large values of N:
Precisely,
should be
0.69RC/2
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Elmore Delay - V
n2
n1
n1
n2
C/2
R
C/2
R=unit wire resistance*length
C=unit wire capacitance*length
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RC Tree Delay
4
4
2
2
7
7
2
24+4*2=32
1
1
Unit wire cap=1, unit wire res=1
3.5
2*(1+3.5+3.5+2+2)=24
RC Tree Delay=max{32,48.5}=48.5
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3.5
2
24+7*3.5=48.5
Precisely,
0.69*48.5
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Summary

Wire capacitance
 Fringing/coupling capacitance dominates area capacitance


Wire resistance
RC Elmore delay model for wire
 For single wire, 0.69RC/2
 RC tree
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