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Digital Integrated
Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
The Devices
July 30, 2002
© Digital Integrated Circuits2nd
Devices
Goal of this chapter
Present intuitive understanding of device
operation
Introduction of basic device equations
Introduction of models for manual
analysis
Introduction of models for SPICE
simulation
Analysis of secondary and deep-submicron effects
Future trends
© Digital Integrated Circuits2nd
Devices
The Diode
B
A
Al
SiO2
p
n
Cross-section of pn-junction in an IC process
A
p
Al
A
n
B
One-dimensional
representation
B
diode symbol
Mostly occurring as parasitic element in Digital ICs
© Digital Integrated Circuits2nd
Devices
Depletion Region
hole diffusion
electron diffusion
(a) Current flow.
n
p
hole drift
electron drift
Charge
Density
x
Distance
+
-
Electrical
Field
(b) Charge density.
x
(c) Electric field.
V
Potential
-W 1
© Digital Integrated Circuits2nd
W2
x
(d) Electrostatic
potential.
Devices
Depletion Region
hole diffusion
electron diffusion
p
(a) Current flow.
n
n N c exp(
p N v exp(
Ec E f
kT
Ev E f
kT
+
x
Distance
(b) Charge density.
qo kT ln(
Eg
x
(c) Electric field.
qo kT ln(
)
Nc Nv
)
ni2
[kT ln(
Nc
N
) kT ln( v )]
nno
p po
nno p po
ni2
) kT ln(
ND N A
)
2
ni
n po p po n po p po ni2
V
Potential
-W 1
)
kT
qo E g (qVn qVp )
-
Electrical
Field
)
np ni2 N c N v exp(
hole drift
electron drift
Charge
Density
np ni2 (1.5 x1010 ) 2
W2
© Digital Integrated Circuits2nd
x
(d) Electrostatic
potential.
o
p po
n
kT
kT
ln(
)
ln( no )
q
pno
q
n po
Devices
Depletion Region
W2 N D W1 N A
hole diffusion
electron diffusion
p
(a) Current flow.
n
For 0 x W2
hole drift
electron drift
Charge
Density
2V ( x)
x 2
s
For 0 x W1
+
x
Distance
(b) Charge density.
2V qN A
2
x
s
For 0 x W1
For 0 x W2
| Emax ( x 0) |
x
(c) Electric field.
V
Potential
W2
© Digital Integrated Circuits2nd
x
(d) Electrostatic
potential.
E ( x)
E ( x)
qN A (W1 )
s
V qN A ( x W1 )
x
s
V qND ( x W2 )
x
s
qND (W2 )
s
Integrating twice...
V ( x) Emax ( x
-W 1
2V qND
x 2
s
Integrating ...
-
Electrical
Field
0
1
EmaxW
2
W
2 s
q
x2
) W W1 W2
2W
N A ND
0
N AND
Devices
pn (W2)
Forward Bias
pn0
Lp
np0
Wp
p-region
-W1 0
W2
Wn
n-region
x
diffusion
Typically avoided in Digital ICs
© Digital Integrated Circuits2nd
Devices
Forward Bias
I D,P
dpn
qAD DP
dx
with linear carrier concetration gradient
pn ( x)
© Digital Integrated Circuits2nd
pn (W2 ) pn 0
x const
Wn W2
Devices
Forward Bias
VD
p(W2 ) pn 0 e t
I DP
pn0 ni2 / ND
VD
pn 0 t
qAD D p
e 1
Wn W2
I D I DP I DN
VD
t
I S e 1
np 0
pn 0
where Is qAD DP
qAD Dn
Wn W2
Wp W1
© Digital Integrated Circuits2nd
Devices
Reverse Bias
pn0
np0
p-region
-W1 0
W2
x
n-region
diffusion
The Dominant Operation Mode
© Digital Integrated Circuits2nd
Devices
Diode Current
© Digital Integrated Circuits2nd
Devices
Models for Manual Analysis
+
ID = IS(eV D/T – 1)
VD
ID
+
+
VD
–
(a) Ideal diode model
© Digital Integrated Circuits2nd
–
VDon
–
(b) First-order diode model
Devices
Junction Capacitance
Q j AD qW2 ( N D ) AD qW1 ( N A )
Q j AD
Cj
dQj
dVd
Cj
2q s N A N D
(0 Vd )
N A ND
AD
C j0
1
© Digital Integrated Circuits2nd
2q s N A N D
(0 Vd ) 1
N A ND
Vd
0
Devices
Diffusion Capacitance
© Digital Integrated Circuits2nd
Devices
Secondary Effects
ID (A)
0.1
0
–0.1
–25.0
–15.0
–5.0
0
5.0
VD (V)
Avalanche Breakdown
© Digital Integrated Circuits2nd
Devices
Diode Model
RS
+
VD
ID
CD
-
© Digital Integrated Circuits2nd
Devices
SPICE Parameters
© Digital Integrated Circuits2nd
Devices
What is a Transistor?
A Switch!
An MOS Transistor
VGS V T
|VGS|
Ron
S
© Digital Integrated Circuits2nd
D
Devices
The MOS Transistor
Polysilicon
© Digital Integrated Circuits2nd
Aluminum
Devices
MOS Transistors Types and Symbols
D
D
G
G
S
S
NMOS Enhancement NMOS Depletion
D
G
G
S
PMOS Enhancement
© Digital Integrated Circuits2nd
D
B
S
NMOS with
Bulk Contact
Devices
Basic Concepts
Vg Vox s
E ( x)
d ( x )
dx
s ( x 0) surface potential
d ( x)
Es E ( x 0)
| x 0
dx
ps and n s are surface carrier concetration
which are of great intrest
© Digital Integrated Circuits2nd
Devices
Depletion of MOS
xd =
2 si
S
qN A
QB 0 qN A xd 2qN A siS
QS QB0 surface charge
VOX
QS
where COX OX
COX
tOX
© Digital Integrated Circuits2nd
Devices
Creating Inversion Layer
F
kT N A
ln
Fermi potential
q
ni
S 2F
xd =
2 si
2 F
qN A
QB 0 2qN A si (2 F )
QS QB0 QI QB0
© Digital Integrated Circuits2nd
Devices
Ideal Threshold Voltage
VG Vox s and VTO VG
VTO
2qN A si (2 F )
QS
S
2 F
COX
COX
© Digital Integrated Circuits2nd
Devices
More Realistic Vto
VTO
2qN A si (2 F )
COX
where VFB GS
2 F VFB
1
(QOX QSS )
COX
flat band voltage due to impurites in oxide and substrate!
© Digital Integrated Circuits2nd
Devices
Even More Realistic Vto
Threshold
VTO
adjustment with ion dose Di
2qN A si (2 F )
© Digital Integrated Circuits2nd
COX
qDi
2 F VFB
COX
Devices
Body Effect
QB 2qN A si (2 F VB )
VT VT VTO
2qN A si
( 2 F VB 2 F )
COX
VT VTO ( 2 F VB 2 F )
2qN A si
COX
© Digital Integrated Circuits2nd
Devices
MOSFET Operation
© Digital Integrated Circuits2nd
Devices
MOSFET GCA Analysis
V ( y) : 0 Vds as y : 0 L
xdm ( y )
2 si
[ 2F V ( y )
qN A
depletion depth increases from y : 0 L !!!
QI ( y) COX [Vgs VT V ( y)]
charge density decreases from y : 0 L!!!
© Digital Integrated Circuits2nd
Devices
MOSFET GCA Analysis
dy
dR
nWQI ( y )
© Digital Integrated Circuits2nd
Devices
MOSFET GCA Analysis
QI ( y ) COX [Vgs VT V ( y )]
dy
dR
nWQI ( y )
I D dy
dV I D dR
nWQI ( y )
L
I D dy nW
0
Vds
Q ( y )dV
I
0
V
W ds
I D nCOX ( ) (Vgs VT V )dV
L 0
© Digital Integrated Circuits2nd
Devices
Non saturation mode
2
Vds
W
I D nCOX ( )[(Vgs VT )Vds
]
L
2
© Digital Integrated Circuits2nd
Devices
Saturation Mode
Find
the maximum in Id equation
dI D
W
nCOX ( )[Vgs VT Vds ] 0
dVds
L
Vds,sat Vgs VT
I D nCOX
© Digital Integrated Circuits2nd
W 1
(Vgs VT ) 2
L 2
Devices
Saturation Mode
QI ( L) COX [Vgs VT Vds ] 0
© Digital Integrated Circuits2nd
Devices
Channel Length Modulation
V ( L ') Vds ,sat
QI ( L ') 0
© Digital Integrated Circuits2nd
L
2 si
(Vds Vdssat )
qN A
Devices
Saturation Mode (Channel Length
Modulation)
1
W
I D nCOX
(Vgs VT ) 2
L
2
L(1
)
L
1
L
1
1 Vds
L
L
(1
)
L
I D nCOX
© Digital Integrated Circuits2nd
W 1
(Vgs VT ) 2 (1 Vds )
L 2
Devices
The Threshold Voltage
© Digital Integrated Circuits2nd
Devices
The Body Effect
0.9
0.85
0.8
0.75
VT (V)
0.7
0.65
0.6
0.55
0.5
0.45
0.4
-2.5
-2
-1.5
-1
V
BS
© Digital Integrated Circuits2nd
-0.5
0
(V)
Devices
Body Bias
© Digital Integrated Circuits2nd
Devices
Current-Voltage Relations
A good ol’ transistor
6
x 10
-4
VGS= 2.5 V
5
Resistive
Saturation
4
ID (A)
VGS= 2.0 V
3
VDS = VGS - VT
2
VGS= 1.5 V
1
0
Quadratic
Relationship
VGS= 1.0 V
0
0.5
1
1.5
2
2.5
VDS (V)
© Digital Integrated Circuits2nd
Devices
Current-Voltage Relations
Long-Channel Device
© Digital Integrated Circuits2nd
Devices
A model for manual analysis
© Digital Integrated Circuits2nd
Devices
Current-Voltage Relations
The Deep-Submicron Era
2.5
x 10
-4
VGS= 2.5 V
Early Saturation
2
VGS= 2.0 V
ID (A)
1.5
VGS= 1.5 V
1
0.5
0
Linear
Relationship
VGS= 1.0 V
0
0.5
1
1.5
2
2.5
VDS (V)
© Digital Integrated Circuits2nd
Devices
Velocity Saturation
ideally un n E
u n (m/s)
o
but n
(1 Vgs )
usat = 105
Constant velocity
Constant mobility (slope = µ)
c = 1.5
© Digital Integrated Circuits2nd
(V/µm)
Devices
Perspective
ID
Long-channel device
VGS = VDD
Short-channel device
V DSAT
© Digital Integrated Circuits2nd
VGS - V T
VDS
Devices
ID versus VGS
-4
6
x 10
-4
x 10
2.5
5
2
4
linear
quadratic
ID (A)
ID (A)
1.5
3
1
2
0.5
1
0
0
quadratic
0.5
1
1.5
VGS(V)
Long Channel
© Digital Integrated Circuits2nd
2
2.5
0
0
0.5
1
1.5
2
2.5
VGS(V)
Short Channel
Devices
ID versus VDS
-4
6
-4
x 10
VGS= 2.5 V
x 10
2.5
VGS= 2.5 V
5
2
Resistive Saturation
ID (A)
VGS= 2.0 V
3
VDS = VGS - VT
2
1
VGS= 1.5 V
0.5
VGS= 1.0 V
VGS= 1.5 V
1
0
0
VGS= 2.0 V
1.5
ID (A)
4
VGS= 1.0 V
0.5
1
1.5
VDS(V)
Long Channel
© Digital Integrated Circuits2nd
2
2.5
0
0
0.5
1
1.5
2
VDS(V)
Short Channel
Devices
2.5
Simple Model versus SPICE
2.5
x 10
-4
VDS=VDSAT
2
Velocity
Saturated
ID (A)
1.5
Linear
1
VDSAT=VGT
0.5
VDS=VGT
0
0
0.5
Saturated
1
1.5
2
2.5
VDS (V)
© Digital Integrated Circuits2nd
Devices
A PMOS Transistor
-4
0
x 10
VGS = -1.0V
-0.2
VGS = -1.5V
ID (A)
-0.4
-0.6
-0.8
-1
-2.5
VGS = -2.0V
Assume all variables
Negative relative to
Vdd!
VGS = -2.5V
-2
-1.5
-1
-0.5
0
VDS (V)
© Digital Integrated Circuits2nd
Devices
Transistor Model
for Manual Analysis
© Digital Integrated Circuits2nd
Devices
MOS Capacitances
Dynamic Behavior
© Digital Integrated Circuits2nd
Devices
Dynamic Behavior of MOS Transistor
G
CGS
CGD
D
S
CGB
CSB
CDB
B
© Digital Integrated Circuits2nd
Devices
The Gate Capacitance
Polysilicon gate
SPICE Parameter:
CGSO, CGDO = Xd*Cox
Source
Drain
xd
n+
xd
Ld
W
n+
Gate-bulk
overlap
Top view
Gate oxide
tox
n+
L
n+
Cross section
© Digital Integrated Circuits2nd
Devices
Gate Capacitance
G
G
CGC
CGC
D
S
G
Cut-off
CGC
D
S
Resistive
D
S
Saturation
Most important regions in digital design: saturation and cut-off
For speed considerations, assume worst-case scenario = W*L*Cox
© Digital Integrated Circuits2nd
Devices
Gate Capacitance
CG C
WLC ox
WLC ox
2
CGC B
C G CS = CG CD
CG C
Capacitance as a function of VGS
(with VDS = 0)
2WLC ox
CG CS
3
WLC ox
CGCD
2
VG S
© Digital Integrated Circuits2nd
WLC ox
0
VDS /(VG S-VT)
1
Capacitance as a function of the
degree of saturation
Devices
Measuring the Gate Cap
x 10-16
10
9
V GS
8
I
7
6
5
C gs
I
dVgs / dt
© Digital Integrated Circuits2nd
4
Gate
3 Capacitance (F)
2
- 2 - 1.5 - 1 - 0.5 0 0.5
V GS (V)
1
1.5
2
Devices
Diffusion Capacitance
Channel-stop implant
N A+
Side wall
Source
ND
W
Bottom
xj
Side wall
LS
© Digital Integrated Circuits2nd
Channel
Substrate N A
Devices
Junction Capacitance
© Digital Integrated Circuits2nd
Devices
Capacitances in 0.25 m CMOS
process
© Digital Integrated Circuits2nd
Devices
Capacitances in 0.5 m CMOS
process
NMOSFET
PMOSFET
K
19.6 uA/V2
5.4 uA/V2
VTO
0.74 V
-0.74 V
0.6
0.6
0.06 V-1
0.19 V-1
Xd (Under Diffusion)
6 nm
1 nm
NSUB
1.3 x 10^(16) cm-3
4.8 x 10^(15) cm-3
COX
1.1 x 10^(-3) F/m
1.1 x 10^(-3) F/m
CGDO = CGSO
9.6 x 10^(-12) F/m
1.7 x 10^(-12) F/m
CJ
2.8 x 10^(-4) F/m2
3.0 x 10^(-4) F/m2
CJSW
1.7 x 10^(-10) F/m
2.6 x 10^(-10) F/m
© Digital Integrated Circuits2nd
Devices
The Sub-Micron MOS Transistor
Threshold
Variations
Subthreshold Conduction
Parasitic Resistances
© Digital Integrated Circuits2nd
Devices
Threshold Variations
VT
VT
Long-channel threshold
L
Threshold as a function of
the length (for low VDS )
© Digital Integrated Circuits2nd
Low VDS threshold
VDS
Drain-induced barrier lowering
(for low L)
Devices
Sub-Threshold Conduction
The Slope Factor
qV gs
-2
10
I D I 0 e nkT (1 e
Linear
for Vds
-4
10
qV gs
-6
and 0
ID (A)
CD
COX
S is VGS for ID2/ID1 =10
-8
10
-10
Exponential
-12
VT
10
10
)(1 Vds )
I D I 0 e nkT , n 1
Quadratic
10
kT
q
qVds
kT
0
0.5
1
1.5
VGS (V)
© Digital Integrated Circuits2nd
2
2.5
Typical values for S:
60 .. 100 mV/decade
Devices
Sub-Threshold ID vs VGS
I D I 0e
qVGS
nkT
qV
DS
1 e kT
VDS from 0 to 0.5V
© Digital Integrated Circuits2nd
Devices
Sub-Threshold ID vs VDS
I D I 0e
qVGS
nkT
qV
DS
1 e kT
1 VDS
VGS from 0 to 0.3V
© Digital Integrated Circuits2nd
Devices
Summary of MOSFET Operating
Regions
Strong
Inversion VGS > VT
Linear (Resistive) VDS < VDSAT
Saturated (Constant Current) VDS VDSAT
Weak
Inversion (Sub-Threshold) VGS VT
Exponential in VGS with linear VDS dependence
© Digital Integrated Circuits2nd
Devices
Parasitic Resistances
Polysilicon gate
LD
G
Drain
contact
D
S
RS
W
VGS,eff
RD
Drain
© Digital Integrated Circuits2nd
Devices
Latch-up
VD D
VDD
+
p
+
n
n+
+
p
+
n+
p
n-well
Rnwell
Rnwell
Rpsubs
n-source
p-substrate
(a) Origin of latchup
© Digital Integrated Circuits2nd
p-source
Rpsubs
(b) Equivalent circuit
Devices
Future Perspectives
25 nm FINFET MOS transistor
© Digital Integrated Circuits2nd
Devices