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Digital Integrated
Circuits
A Design Perspective
The Wire
July 30, 2002
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The Wire
receivers
transmitters
schematics
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physical
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2
Wire Models
All-inclusive model
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Capacitance-only
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Impact of Interconnect Parasitics
 Interconnect
parasitics
 reduce reliability
 affect performance and power consumption
 Classes
of parasitics
 Capacitive
 Resistive
 Inductive
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Nature of Interconnect
No of nets
(Log Scale)
Local Interconnect
Pentium Pro (R)
Pentium(R) II
Pentium (MMX)
Pentium (R)
Pentium (R) II
Global Interconnect
SGlobal = SDie
Source: Intel
SLocal = STechnology
10
100
1,000
10,000
100,000
Length (u)
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Capacitance
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Capacitance: The Parallel Plate Model
Current flow
L
Electrical-field lines
W
Permittivity
H
tdi
Dielectric
Substrate
cint 
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 di
t di
WL
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Fringing Capacitance
(a)
H
W - H/2
+
(b)
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Fringing versus Parallel Plate


The larger value of W/H,
the total cap approaches
the parallel plate model.
For small W/H, the
fringing component
becomes dominant (by a
factor of more than 10).
(from [Bakoglu89])
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Interwire Capacitance
fringing
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Resistance
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Wire Resistance
R= L
HW
Sheet Resistance
Ro
L
H
R1
W
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R2
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Resistivity and Sheet resistance
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Dealing with Resistance
 Selective
Technology Scaling
 Use Better Interconnect Materials
 reduce average wire-length
 e.g. copper, silicides
 More
Interconnect Layers
 reduce average wire-length
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Silicide
PolySilicon
SiO2
n+
p
n+
Polycide Gate MOSFET
8-10 times better than Poly
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Interconnect
Modeling
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The Lumped Model
Vout
cwi re
Driver
Rdriver
Vout
Vin
Clumped
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Clump = L*Cwire
L = wire length
Cwire = cap per unit length
Simple, yet effective. So,
the choice for the
analysis in digital IC
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The Elmore Delay: Lumped RC-Model
Branches
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The Ellmore Delay: RC Chain
No branch
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Wire Model: RC Chain model
Assume: Wire length L, modeled by N equal-length segments
r = resistance per unit length,
c = capacitance per unit length
For large values of N:
let R = rL, C= cL (Lumped resistance and lumped
capacitance of the wire)
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Step Response of Lumped and
Distributed RC model
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Example: Driving an RC-line
Rs
(r w,cw,L)
Vout
Vin
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Design Rules of Thumb
rc delays should only be considered when
tpRC >> tpgate of the driving gate
Lcrit >>  tpgate/0.38rc
 rc delays should only be considered when the
rise (fall) time at the line input is smaller than
RC, the rise (fall) time of the line
trise < RC

 when not met, the change in the signal is slower
than the propagation delay of the wire, the lumped
model then suffices.
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