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Digital Integrated
Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
The Wire
July 30, 2002
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The Wire
receivers
transmitters
schematics
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Interconnect Impact on Chip
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Wire Models
All-inclusive model
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Capacitance-only
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Impact of Interconnect Parasitics
 Interconnect
parasitics
 reduce reliability
 affect performance and power consumption
 Classes
of parasitics
 Capacitive
 Resistive
 Inductive
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Nature of Interconnect
No of nets
(Log Scale)
Local Interconnect
Pentium Pro (R)
Pentium(R) II
Pentium (MMX)
Pentium (R)
Pentium (R) II
Global Interconnect
SGlobal = SDie
Source: Intel
SLocal = STechnology
10
100
1,000
10,000
100,000
Length (u)
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INTERCONNECT
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Capacitance of Wire Interconnect
VDD
VDD
M2
Vin
Cg4
Cdb2
Cgd12
M4
Vout
Cdb1
Cw
M1
Vout2
Cg3
M3
Interconnect
Fanout
Simplified
Model
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Vin
Vout
CL
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Capacitance: The Parallel Plate Model
Current flow
L
Electrical-field lines
W
H
tdi
Dielectric
Substrate
cint 
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 di
t di
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SCwire 
S
1

S  SL SL
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Permittivity
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Fringing Capacitance
(a)
H
W - H/2
+
(b)
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Fringing versus Parallel Plate
(from [Bakoglu89])
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Interwire Capacitance
fringing
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Impact of Interwire Capacitance
(from [Bakoglu89])
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Wiring Capacitances (0.25 mm CMOS)
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INTERCONNECT
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Wire Resistance
R= L
HW
Sheet Resistance
Ro
L
H
R1
W
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Interconnect Resistance
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Dealing with Resistance
 Selective
Technology Scaling
 Use Better Interconnect Materials
 reduce average wire-length
 e.g. copper, silicides
 More
Interconnect Layers
 reduce average wire-length
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Polycide Gate MOSFET
Silicide
PolySilicon
SiO2
n+
n+
p
Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi
Conductivity: 8-10 times better than Poly
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Sheet Resistance
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Modern Interconnect
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Example: Intel 0.25 micron Process
5 metal layers
Ti/Al - Cu/Ti/TiN
Polysilicon dielectric
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INTERCONNECT
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Interconnect
Modeling
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The Lumped Model
Vout
cwi re
Driver
Rdriver
Vout
Vin
Clumped
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The Lumped RC-Model
The Elmore Delay
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The Ellmore Delay
RC Chain
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Wire Model
Assume: Wire modeled by N equal-length segments
For large values of N:
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The Distributed RC-line
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Step-response of RC wire as a
function of time and space
2.5
x= L/10
2
voltage (V)
x = L/4
1.5
x = L/2
1
x= L
0.5
0
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1.5
2
2.5
3
time (nsec)
3.5
4
4.5
5
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RC-Models
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Driving an RC-line
Rs
(r w,cw,L)
Vout
Vin
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Design Rules of Thumb
rc delays should only be considered when
tpRC >> tpgate of the driving gate
Lcrit >>  tpgate/0.38rc
 rc delays should only be considered when the
rise (fall) time at the line input is smaller than
RC, the rise (fall) time of the line
trise < RC

 when not met, the change in the signal is slower
than the propagation delay of the wire
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