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IEP on Synthesis of Digital Design 2007
Adder Circuits
Adder Circuits
S. Sundar Kumar Iyer
1
IEP on Synthesis of Digital Design 2007
Adder Circuits
Acknowledgement
Slides taken from
http://bwrc.eecs.berkeley.edu/IcBook/index.htm
which is the web-site of “Digital Integrated Circuit – A Design
Perspective” by Rabaey, Chandrakasan, Nicolic
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Outline
Background
Ripple
/ Basics of Adders
Carry Adder
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Adder Circuits
IEP on Synthesis of Digital Design 2007
A Generic Digital Processor
INPUT-OUTPUT
MEM ORY
CONTROL
DATAPATH
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IEP on Synthesis of Digital Design 2007
Adder Circuits
Building Blocks for Digital Architectures
Arithmetic unit
- Bit-sliced datapath (adder, multiplier, shifter, comparator, etc.)
Memory
- RAM, ROM, Buffers, Shift registers
Control
- Finite state machine (PLA, random logic.)
- Counters
Interconnect
- Switches
- Arbiters
- Bus
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Bit-Sliced Design
Control
Bit 2
Bit 1
Data-Out
Multiplexer
Shifter
Adder
Register
Data-In
Bit 3
Bit 0
Tile identical processing elements
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Bit-Sliced Datapath
From register files / Cache / Bypass
Multiplexers
Shifter
Adder stage 1
Adder stage 2
Wiring
Bit slice 0
Bit slice 1
Bit slice 2
Bit slice 63
Adder stage 3
Loopback Bus
Loopback Bus
Loopback Bus
Wiring
Sum Select
To register files / Cache
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IEP on Synthesis of Digital Design 2007
Adder Circuits
Itanium Integer Datapath
Fetzer, Orton, ISSCC’02
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Full-Adder
A
Cin
B
Full
adder
Cout
Sum
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Adder Circuits
IEP on Synthesis of Digital Design 2007
The Binary Adder
A
Cin
B
Full
adder
Cout
Sum
S = A B Ci
= ABC i + ABC i + ABCi + ABCi
C o = AB + BC i + ACi
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IEP on Synthesis of Digital Design 2007
Adder Circuits
Express Sum and Carry as a function of P, G, D
Define 3 new variable which ONLY depend on A, B
Generate (G) = AB
Propagate (P) = A B
Delete = A B
Can also derive expressions for S and Co based on D and P
Note that we will be sometimes using an alternate definition for
Propagate (P) = A + B
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Adder Circuits
IEP on Synthesis of Digital Design 2007
The Ripple-Carry Adder
A0
B0
Ci,0
A1
B1
Co,0
FA
A2
B2
Co,1
A3
B3
Co,2
Co,3
FA
FA
FA
S1
S2
S3
(= Ci,1)
S0
Worst case delay linear with the number of bits
td = O(N)
tadder = (N-1)tcarry + tsum
Goal: Make the fastest possible carry path circuit
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Complimentary Static CMOS Full Adder
VDD
VDD
A
Ci
A
B
B
A
B
B
Ci
A
X
Ci
VDD
Ci
S
A
Ci
A
B
B
VDD
A
B
Co
Ci
A
B
28 Transistors
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Inversion Property
A
Ci
A
B
FA
S
Co
Ci
B
FA
Co
S
S A B C i = S A B Ci
C A B C = C A B C
o
i
o
i
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Minimize Critical Path by Reducing Inverting Stages
Even cell
A0
B0
Ci,0
A1
B1
Co,0
A2
Odd cell
B2
Co,1
A3
B3
Co,2
Co,3
FA
FA
FA
FA
S0
S1
S2
S3
Exploit Inversion Property
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Adder Circuits
IEP on Synthesis of Digital Design 2007
A Better Structure: The Mirror Adder
VDD
VDD
A
B
VDD
A
B
B
Ci
A
B
Kill
"0"-Propagate
A
Ci
Co
Ci
S
Ci
A
"1"-Propagate
Generate
A
B
B
A
B
Ci
A
B
24 transistors
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Mirror Adder
Stick Diagram
VDD
A
B
Ci
B
A Ci
Co
Ci
A
B
Co
S
GND
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IEP on Synthesis of Digital Design 2007
Adder Circuits
The Mirror Adder
•The NMOS and PMOS chains are completely symmetrical.
A maximum of two series transistors can be observed in the carrygeneration circuitry.
•When laying out the cell, the most critical issue is the minimization
of the capacitance at node Co. The reduction of the diffusion
capacitances is particularly important.
•The capacitance at node Co is composed of four diffusion
capacitances, two internal gate capacitances, and six gate
capacitances in the connecting adder cell .
•The transistors connected to Ci are placed closest to the output.
•Only the transistors in the carry stage have to be optimized for
optimal speed. All transistors in the sum stage can be minimal
size.
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Transmission Gate Full Adder
P
VDD
Ci
A
P
A
A
P
B
VDD
Ci
A
P
Ci
VDD
S Sum Generation
Ci
P
B
VDD
A
P
Co Carry Generation
Ci
A
Setup
P
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Manchester Carry Chain
VDD
Pi
VDD
Pi
Co
Ci
Gi
Co
Ci
Gi
Di
Pi
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Manchester Carry Chain
VDD
P0
P1
P2
P3
C3
Ci,0
G1
G0
G3
G2
C0
C1
C2
C3
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Manchester Carry Chain
Stick Diagram
Propagate/Generate Row
VDD
Pi
Ci - 1
Gi
Pi + 1
Gi + 1
Ci
Ci + 1
GND
Inverter/Sum Row
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Carry-Bypass Adder
G1
Ci,0
P0
G1
C o,0
P0
FA
P2
Also called
Carry-Skip
FA
G2
Co,1
FA
G3
Co,3
FA
G1
C o,0
P3
Co,2
FA
P0 G1
G2
C o,1
FA
Ci,0
P2
P3
G3
BP=P oP1 P2 P3
C o,2
FA
FA
Multiplexer
P0
Co,3
Idea: If (P0 and P1 and P2 and P3 = 1)
then C o3 = C 0, else “kill” or “generate”.
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Carry-Bypass Adder (cont.)
Bit 0–3
Bit 4–7
Setup
tsetup
Setup
tbypass
Bit 8–11
Bit 12–15
Setup
Setup
Carry
propagation
Carry
propagation
Carry
propagation
Carry
propagation
Sum
Sum
Sum
tsum
Sum
M bits
tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Carry Ripple versus Carry Bypass
tp
ripple adder
bypass adder
4..8
N
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Carry-Select Adder
Setup
P,G
Co,k-1
"0"
"0" Carry Propagation
"1"
"1" Carry Propagation
Multiplexer
Co,k+3
Carry Vector
Sum Generation
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Carry Select Adder: Critical Path
Bit 0–3
Bit 4–7
Bit 8–11
Bit 12–15
Setup
Setup
Setup
Setup
0
0-Carry
0
0-Carry
0
0-Carry
0
0-Carry
1
1-Carry
1
1-Carry
1
1-Carry
1
1-Carry
Ci,0
Multiplexer
Co,3
Multiplexer
Co,7
Multiplexer
Co,11
Multiplexer
Sum Generation
Sum Generation
Sum Generation
Sum Generation
S0–3
S4–7
S8–11
S12–15
Co,15
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Linear Carry Select
Bit 0-3
Bit 4-7
Setup
Setup
Bit 8-11
Bit 12-15
Setup
Setup
(1)
"0" Carry
"0"
"0"
"0" Carry
"0"
"0" Carry
"0"
"0" Carry
(1)
"1" Carry
"1"
"1" Carry
"1"
(5)
(5)
(5)
(6)
Multiplexer
"1" Carry
"1"
(5)
(7)
Multiplexer
"1" Carry
"1"
(5)
(8)
Multiplexer
Ci,0
Multiplexer
(9)
Sum Generation
S0-3
Sum Generation
Sum Generation
S 4-7
S8-11
Sum Generation
S 12-15 (10)
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Square Root Carry Select
Bit 0-1
Bit 2-4
Setup
Setup
Bit 5-8
Bit 9-13
Setup
Setup
Bit 14-19
(1)
"0" Carry
"0"
"0"
"0" Carry
"0"
"0" Carry
"0"
"0" Carry
(1)
"1" Carry
"1"
(3)
"1" Carry
"1"
(3)
(4)
(4)
Multiplexer
"1" Carry
"1"
(5)
(5)
Multiplexer
"1" Carry
"1"
(6)
Multiplexer
(7)
(6)
(7)
Multiplexer
Mux
Ci,0
(8)
Sum Generation
S0-1
Sum Generation
Sum Generation
S2-4
S5-8
Sum Generation
S9-13
Sum
S14-19 (9)
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Adder Delays - Comparison
50
Ripple adder
tp (in unit delays)
40
30
Linear select
20
10
0
Square root select
0
20
40
60
N
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Adder Circuits
IEP on Synthesis of Digital Design 2007
LookAhead - Basic Idea
A0, B0
Ci,0
A1, B1
P0 Ci,1
S0
•••
P1
S1
AN-1, BN-1
Ci, N-1
•••
PN-1
SN-1
C o k = f A k B k Co k – 1 = Gk + P kCo k – 1
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Look-Ahead: Topology
Expanding Lookahead equations:
VDD
C o k = Gk + Pk Gk – 1 + Pk – 1Co k – 2
G3
G2
All the way:
G1
C o k = Gk + Pk Gk – 1 + P k – 1 + P1 G0 + P0 Ci 0
G0
Ci,0
Co,3
P0
P1
P2
P3
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Logarithmic Look-Ahead Adder
F
A0
A1
A2
A3
A4
A5
A6
A7
tp N
A0
A1
A2
A3
F
A4
A5
A6
A7
tp log2(N)
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Carry Lookahead Trees
Co 0 = G0 + P0 Ci 0
C o 1 = G1 + P1 G0 + P1 P0 Ci 0
C o 2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C i 0
= G2 + P2 G1 + P2 P1 G0 + P0 Ci 0 = G 2:1 + P2:1 C o 0
Can continue building the tree hierarchically.
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S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
(A0, B0)
(A1, B1)
(A2, B2)
(A3, B3)
(A4, B4)
(A5, B5)
(A6, B6)
(A7, B7)
(A8, B8)
(A9, B9)
(A10, B10)
(A11, B11)
(A12, B12)
(A13, B13)
(A14, B14)
(A15, B15)
IEP on Synthesis of Digital Design 2007
Adder Circuits
Tree Adders
16-bit radix-2 Kogge-Stone tree
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S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S 10
S 11
S 12
S 13
S 14
S 15
(a 0, b 0)
(a 1, b 1)
(a 2, b 2)
(a 3, b 3)
(a 4, b 4)
(a 5, b 5)
(a 6, b 6)
(a 7, b 7)
(a 8, b 8)
(a 9, b 9)
(a 10, b 10)
(a 11, b 11)
(a 12, b 12)
(a 13, b 13)
(a 14, b 14)
(a 15, b 15)
IEP on Synthesis of Digital Design 2007
Adder Circuits
Tree Adders
16-bit radix-4 Kogge-Stone Tree
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S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S 10
S 11
S 12
S 13
S 14
S 15
(a 0, b 0)
(a 1, b 1)
(a 2, b 2)
(a 3, b 3)
(a 4, b 4)
(a 5, b 5)
(a 6, b 6)
(a 7, b 7)
(a 8, b 8)
(a 9, b 9)
(a 10, b 10)
(a 11, b 11)
(a 12, b 12)
(a 13, b 13)
(a 14, b 14)
(a 15, b 15)
IEP on Synthesis of Digital Design 2007
Adder Circuits
Sparse Trees
16-bit radix-2 sparse tree with sparseness of 2
37
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
(A0, B0)
(A1, B1)
(A2, B2)
(A3, B3)
(A4, B4)
(A5, B5)
(A6, B6)
(A7, B7)
(A8, B8)
(A9, B9)
(A10, B10)
(A11, B11)
(A12, B12)
(A13, B13)
(A14, B14)
(A15, B15)
IEP on Synthesis of Digital Design 2007
Adder Circuits
Tree Adders
Brent-Kung Tree
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Example: Domino Adder
VDD
VDD
Clk
Clk
Pi= ai + bi
ai
bi
Gi = aibi
ai
bi
Clk
Clk
Propagate
Generate
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Adder Circuits
IEP on Synthesis of Digital Design 2007
Example: Domino Adder
VDD
VDD
Clkk
Clkk
Gi:i-2k+1
Pi:i-2k+1
Pi:i-k+1
Pi:i-k+1
Gi:i-k+1
Pi-k:i-2k+1
Propagate
Gi-k:i-2k+1
Generate
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IEP on Synthesis of Digital Design 2007
Adder Circuits
Example: Domino Sum
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