Transcript The GAL16V8 PLD - Oakland University

Designing Combinational Logic
Circuits in Verilog - 1
Discussion 7.1
Designing Combinational Logic
Circuits in Verilog - 1
•
•
•
•
Gates
Multiplexers
Adder
Subtractor
Hardware Description Languages
• Verilog
• ABEL
• VHDL
We will only cover Verilog
VHDL is taught in CSE 378
Verilog
gates.v
Verilog source code
module gates(x,y,invx,invy,andd,orr,nandd,norr,xorr,xnorr);
input x;
input y;
output invx;
output invy;
output andd;
output orr;
output nandd;
output norr;
output xorr;
output xnorr;
assign
assign
assign
assign
assign
assign
assign
assign
endmodule
invx = ~x;
invy = ~y;
andd = x & y;
orr = x | y;
nandd = ~(x & y);
norr = ~(x | y);
xorr = x ^ y;
xnorr = x ~^ y;
Pin numbers set it separate file:
gates.ucf
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"x"
"y"
"invx"
"invy"
"andd"
"nandd"
"orr"
"norr"
"xorr"
"xnorr"
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
=
=
=
=
=
=
=
=
=
=
"p11";
"p7";
"p35";
"p36";
"p37";
"p39";
"p40";
"p41";
"p43";
"p44";
module gates ( X ,Z, Y );
Gates.v
input [4:1] X ;
wire [4:1] X ;
output [6:1]
wire [6:1] Z
output [6:1]
wire [6:1] Y
Z ;
;
Y ;
;
and(Z[6],X[1],X[2],X[3],X[4]);
nand(Z[5],X[1],X[2],X[3],X[4]);
or(Z[4],X[1],X[2],X[3],X[4]);
nor(Z[3],X[1],X[2],X[3],X[4]);
xor(Z[2],X[1],X[2],X[3],X[4]);
xnor(Z[1],X[1],X[2],X[3],X[4]);
assign
assign
assign
assign
assign
assign
Y[6]
Y[5]
Y[4]
Y[3]
Y[2]
Y[1]
endmodule
=
=
=
=
=
=
&X;
~&X;
|X;
~|X;
^X;
~^X;
Verilog gate level primitives
Verilog reduction operators
and(Z[6],X[1],...
nand(Z[5],X[1], ..
or(Z[4],X[1], ...
nor(Z[3],X[1], ...
xor(Z[2],X[1], ...
xnor(Z[1],X[1], ..
assign
assign
assign
assign
assign
assign
Y[6]
Y[5]
Y[4]
Y[3]
Y[2]
Y[1]
=
=
=
=
=
=
&X;
~&X;
|X;
~|X;
^X;
~^X;
Implementing Combinational
Logic Circuits in Verilog
•
•
•
•
Gates
Multiplexers
Adder
Subtractor
Multiplexers
C0
C1
C2
C3
4x1
MUX
s1 s0
Y
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
Multiplexers
4x1
MUX
C0
C1
C2
C3
Y
s1 s0
0 0
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
A multiplexer is a
digital switch
Multiplexers
4x1
MUX
C0
C1
C2
C3
Y
s1 s0
0 1
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
Multiplexers
4x1
MUX
C0
C1
C2
C3
Y
s1 s0
1 0
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
Multiplexers
4x1
MUX
C0
C1
C2
C3
Y
s1 s0
1 1
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
A 2 x 1 MUX
A
2x1
MUX
B
Z
s0
Z
0
A
1
B
s0
Z = A & ~s0 | B & s0
A 4 x 1 MUX
C0
2x1
MUX
C1
A
A = ~s0 & C0 | s0 & C1
2x1
MUX
s0
B = ~s0 & C2 | s0 & C3
B
C2
2x1
MUX
Z = ~s1 & A | s1 & B
C3
Z = ~s1 & (~s0 & C0 | s0 & C1)
| s1 & (~s0 & C2 | s0 & C3)
s0
s1
Z
A 4 x 1 MUX
Z = ~s1 & (~s0 & C0 | s0 & C1)
| s1 & (~s0 & C2 | s0 & C3)
s1 s0
C0
C1
C2
4x1
MUX
C3
s1 s0
Z
0
0
1
1
0
1
0
1
Z = ~s1 & ~s0 &
Z | ~s1 & s0 &
| s1 & ~s0 &
C0 | s1 & s0 &
C1
C2
C3
C0
C1
C2
C3
A 4 x 1 MUX
s1 s0
C0
C1
C2
4x1
MUX
C3
s1 s0
Z
0
0
1
1
0
1
0
1
Z
C0
C1
C2
C3
case(s)
2'b00 :
2'b01 :
2'b10 :
2'b11 :
default:
endcase
Z
Z
Z
Z
Z
=
=
=
=
=
C0;
C1;
C2;
C3;
C0;
Problem
How would you make a
Quad 2-to-1 MUX?
[A3..A0]
[B3..B0]
Quad
2-to-1
MUX
s
[Y3..Y0]
s
Y
0
1
A
B
mux.v
module mux24(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
wire [3:0] Y;
assign Y = {4{~s}} & A | {4{s}} & B;
endmodule
[A3..A0]
[B3..B0]
Quad
2-to-1
MUX
s
[Y3..Y0]
module mux24(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
wire [3:0] Y;
assign Y = {4{~s}} & A | {4{s}} & B;
endmodule
mux.v
module mux24a(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
reg [3:0] Y;
always @(A,B,s)
if(s == 0)
Y = A;
else
Y = B;
endmodule
[A3..A0]
[B3..B0]
Quad
2-to-1
MUX
s
[Y3..Y0]
module mux24a(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
reg [3:0] Y;
always @(A,B,s)
if(s == 0)
Y = A;
else
Y = B;
endmodule
mux.v
module mux24(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
wire [3:0] Y;
assign Y = s ? B : A;
endmodule
[A3..A0]
[B3..B0]
Quad
2-to-1
MUX
s
[Y3..Y0]
Implementing Combinational
Logic Circuits in Verilog
•
•
•
•
Gates
Multiplexers
Adder
Subtractor
Half Adder
A0
B0
A0 B0 S0 C 1
0
0
1
1
0
1
0
1
0
1
1
0
0
0
0
1
S0
C1
Dec Binary
1
+1
2
1
+1
10
Multiple-bit Addition
A3 A2 A1 A0
B3 B2 B1 B0
A 0 1 0 1
A
B
B 0 1 1 1
1
0
0
1
1
1
1
1
1
0 1
1 1
0 0
Ci+1 +Ci
Ai
+Bi
Si
Full Adder
Ci Ai Bi Si Ci+1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
AiBi
00
Ci
11
1
0
1
01
10
1
1
1
Si
Full Adder
Ci Ai Bi Si Ci+1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
Si =
|
|
|
~Ci & ~Ai & Bi
~Ci & Ai & ~Bi
Ci & ~Ai & ~Bi
Ci & Ai & Bi
Full Adder
Si = ~Ci & ~Ai & Bi
| ~Ci & Ai & ~Bi
| Ci & ~Ai & ~Bi
| Ci & Ai & Bi
Si = ~Ci & (~Ai & Bi | Ai & ~Bi)
| Ci & (~Ai & ~Bi | Ai & Bi)
Si = ~Ci & (Ai ^ Bi)
| Ci & (Ai ~^ Bi)
Si = Ci ^ (Ai ^ Bi)
Full Adder
Ci Ai Bi Si Ci+1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
AiBi
00
Ci
01
10
1
0
1
11
1
1
Ci+1
1
Full Adder
Ci Ai Bi Si Ci+1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
AiBi
00
Ci
01
10
1
0
1
11
1
1
1
Ci+1
Ci+1 = Ai & Bi
| Ci & Bi
| Ci & Ai
Full Adder
Ci Ai Bi Si Ci+1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
AiBi
00
Ci
01
10
1
0
1
11
1
1
1
Ci+1
Ci+1 = Ai & Bi
| Ci & ~Ai & Bi
| Ci & Ai & ~Bi
Full Adder
Ci+1 = Ai & Bi
| Ci & ~Ai & Bi
| Ci & Ai & ~Bi
Ci+1 = Ai & Bi
| Ci & (~Ai & Bi | Ai & ~Bi)
Ci+1 = Ai & Bi | Ci & (Ai ^ Bi)
Recall:
Si = Ci ^ (Ai ^ Bi)
Ci+1 = Ai & Bi | Ci & (Ai ^ Bi)
Full Adder
Si = Ci ^ (Ai ^ Bi)
Ci+1 = Ai & Bi | Ci & (Ai ^ Bi)
Ci
Ai
Si
Bi
C i+1
Half-adder
Half-adder
Full Adder
Ci
Ai
Bi
S
half-adder
Si
C
half-adder
C
A full adder can be made from
two half adders (plus an OR gate).
C i+1
Full Adder
Ai
C i+1
Bi
Full Adder
Si
Block Diagram
Ci
4-Bit Adder
A3
B3
A2
Full Adder
Full Adder
4
S3
B1
S
1
0
0
1
1
1
1
1
1
0
1
0
B0
Full Adder
C0
C1
S2
C
A
B
S
A0
Full Adder
C2
C3
C
A1
B2
0
1
1
0
1
S
0
0
adder4.v
module adder4(A,B,S,Cout);
input [3:0] A;
A3 B 3
input [3:0] B;
output [3:0] S;
Full Adder
output Cout;
wire [3:0] S;
wire [4:0] C;
assign C[0]
C
4
= 0;
S3
A2
A1
B2
Full Adder
B1
Full Adder
C2
C3
S2
B0
Full Adder
C0
C1
S
1
// zero carry in
assign S = A ^ B ^ C[3:0];
assign C[4:1] = A & B | (A ^ B) & C[3:0];
assign Cout = C[4];
endmodule
A0
S
0
0
adder4.v
module adder4(A,B,S);
input [3:0] A;
input [3:0] B;
output [3:0] S;
reg [3:0] S;
always @(A, B)
begin
S = A + B;
end
endmodule
4-Bit Adder
A3
B3
A2
Full Adder
Full Adder
4
S3
B1
S
1
0 1
0 0
1 0
B0
Full Adder
C0
C1
S2
C
0:A
0:B
C4:S
A0
Full Adder
C2
C3
C
A1
B2
1
1
1
1
S
1
1
0
1
0
0
1
1
0
0
0
module adder4(A,B,S,carry);
input [3:0] A;
A3 B 3
input [3:0] B;
output [3:0] S;
Full Adder
output carry;
reg [3:0] S;
reg carry;
reg [4:0] temp;
C
4
S3
adder.v
A2
A1
B2
Full Adder
B1
Full Adder
C2
C3
S2
A0
B0
Full Adder
C0
C1
S
1
S
0
Note: In the sensitivity list a
comma can be used in place of
or in Verilog 2001
always @(A, B)
begin
temp = {1'b0,A} + {1'b0,B};
S = temp[3:0];
carry = temp[4];
Concatenate a leading 0
end
endmodule
0
4-Bit Adder
Implementing Combinational
Logic Circuits in Verilog
•
•
•
•
Gates
Multiplexers
Adder
Subtractor
Half Subtractor
A0 B0 D0
0
0
1
1
0
1
0
1
0
1
1
0
A0
B0
C1
0
1
0
0
1 2
0
-1
1
D0
C1
Multiple-bit Subtraction
A3 A2 A1 A0
A 0 1 0 1
1
A 0
B 0
1 1
B3 B2 B1 B0
B 0 1 1 1
1
1 0 1
1 1 1
1 1 0
Ci+1 - Ci
Ai
- Bi
Di
Full Subtractor
Ci Ai Bi Di Ci+1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
0
0
1
1
0
1
AiBi
00
Ci
11
1
0
1
01
10
1
1
1
Di
Di = Ci ^ (Ai ^ Bi)
Same as Si in full adder
Full Subtractor
Ci Ai Bi Di Ci+1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
0
0
1
1
0
1
AiBi
00
Ci
11
10
1
0
1
01
1
1
1
Ci+1
Ci+1 = ~Ai & Bi
| Ci & ~Ai & ~Bi
| Ci & Ai & Bi
Full Subtractor
Ci+1 = ~Ai & Bi
| Ci & ~Ai & ~Bi
| Ci & Ai & Bi
Ci+1 = ~Ai & Bi
| Ci & (~Ai & ~Bi | Ai & Bi)
Ci+1 = ~Ai & Bi | Ci & ~(Ai ^ Bi)
Recall:
Di = Ci ^ (Ai ^ Bi)
Ci+1 = ~Ai & Bi | Ci & ~(Ai ^ Bi)
Full Subtractor
Di = Ci ^ (Ai ^ Bi)
Ci+1 = ~Ai & Bi | Ci & ~(Ai ^ Bi)
Ci
Ai
Di
Bi
C i+1
half subtractor
half subtractor
sub4.v
module sub4(A,B,D,Cout);
input [3:0] A;
input [3:0] B;
output [3:0] D;
output Cout;
wire [3:0] D;
wire [4:0] C;
assign C[0]
= 0;
// zero borrow in
assign D = A ^ B ^ C[3:0];
assign C[4:1] = ~A & B | ~(A ^ B) & C[3:0];
assign Cout = C[4];
endmodule
sub4.v
module sub4(A,B,D);
input [3:0] A;
input [3:0] B;
output [3:0] D;
reg [3:0] D;
always @(A, B)
begin
D = A - B;
end
endmodule
Adder/Subtractor
Full Adder
Reordered
Full Adder
Full
Subtractor
Ci Ai Bi Si Ci+1
Ci Ai Bi Si Ci+1
Ci Ai Bi Di Ci+1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
1
0
0
1
0
NOT
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
0
0
1
1
0
1
Making a full subtractor
from a full adder
Bi
Ai
C i+1
Full Adder
Di
Ci
Adder/Subtractor
A3
B3
A2
B2
A1
B1
A0 B 0
E
Full Adder
C3
C4
SD3
Full Adder
Full Adder
C2
SD2
Full Adder
C1
SD1
E = 0: 4-bit adder
E = 1: 4-bit subtractor
SD0
4-bit Subtractor: E = 1
A3
B3
A2
B2
A1
B1
A0 B 0
E
Full Adder
C3
C4
SD3
Full Adder
Full Adder
C2
SD2
Full Adder
+1
C1
SD1
SD0
Add A to !B (one’s complement) plus 1
That is, add A to two’s complement of B
D=A-B