Transcript Digital Image Processing

EE4OI5
Engineering Design
Chapter 1: The 15 minutes design
Figure 1.1 The Altera UP 3 FPGA Development board
The Altera UP 1 development board.
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+5V
+5V
+5V
PB1
PB2
Altera
Flex
Device
LED
Connections between the pushbuttons, the LEDs, and the
Altera FLEX device.
• The pushbuttons and LED are “active low” (connect zero volt to
the pins when they are pushed)
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Problem Definition
• Build a circuit that turns on the decimal point LED
when one OR the other push button is pushed. i.e.
LED = PB1 + PB2
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• Since the pushbuttons generate inverted (active low) signals
and LED requires inverted signal to turn on, we built an OR
gate with inverted inputs and output.
• This form of the OR gate is also called as “negative logic”
OR gate.
Equivalent circuits for ORing active low inputs and outputs.
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Table 1.1 Hardwired connections on the FPGA chips for the design.
UP 3 Pin Number Connections
UP 1 & UP 2 Pin Number Connections
I/O Device
PB1
PB2
LED
62 (SW7)
48 (SW4)
56 (D3)
28 (FLEX PB1)
29 (FLEX PB2)
14 (7Seg LED DEC. PT.)
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Design
Compilation
Simulation
Verifcation
Graphical Entry
Timing Diagram
Program CPLD
Compiler
HDL Entry
Timing Analysis
UP 1 Development Board
Design process for schematic or VHDL entry.
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Simple design example
• Switch to Quartus II and follow the example in CAD tool!
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