IP Core Design Patrick Longa Outline Intellectual Property (IP) Core: basics IP Core classification IP Core standardization Standard buses/interfaces for IP Cores
Download ReportTranscript IP Core Design Patrick Longa Outline Intellectual Property (IP) Core: basics IP Core classification IP Core standardization Standard buses/interfaces for IP Cores
IP Core Design Patrick Longa Outline Intellectual Property (IP) Core: basics IP Core classification IP Core standardization Standard buses/interfaces for IP Cores IP Cores in the market Example with FIR Filter Compiler IP Core: basics Intellectual Property (IP) core: “Macro” structures with specific industrial-standard function that can be flexibly be adapted and reused in SoC designs. From “sea of cells” to “sea of hard macros” * Figures extracted from [2]. IP Core classification Hard core Soft core Structure Pre-defined organization. Behavioural source code, technology independent. Modelling Modeled as a library component. Synthesizable with several technologies. Flexibility Cannot be modified by the designer. Can be modified by the designer. Timing closure Timing ensured. Timing not guaranteed. IP protection Strong. Usually corresponds to a layout. Weak. Source code. Example FPGA Bitstream. GDSII file for IC layout. VHDL, Verilog. Criteria Classification IP Classification: hard cores and soft cores * Partially extracted from [1]. IP Core standardization VSI Alliance (VSIA) Open, international organization Specify standards for IP and reuse in SoC designs Quality IP (QIP) Metric v2.0 Open Measure of Reuse Excellence (OpenMORE) assessment program Donated by Mentor Graphics / Synopsys to VSIA Evaluate the reusability level of hard/soft IP cores Open Core Protocol International Partnership (OCP-IP) Non-profit organization that promotes the Open Core Protocol (OCP) Specify standards for IP cores in SoC designs Payment to have access to specifications Structure for Packaging, Integrating and Re-using IP within Tool-flows (Spirit) Consortium Create standards for IP interoperability: Standard for describing IP cores Standard for creating an IP tool integration API IP Core standardization Technology-dependent company-based certifications: Altera SOPC Builder ready AMPP Approved Stamp Xilinx AllianceCore qualification Lattice ISPLeverCore Approved Standard bus/interface for IP Cores Wishbone: created by Silicore Open bus/interface for IP cores in SoC designs. Supports 8,16, 32 and 64-bit data bus, synchronous. Free of charge. Advanced Microcontroller Bus Architecture (AMBA): created by ARM Supports 32, 64 and 128-bit data bus with 32-bit address bus. Includes 3 buses: Advanced High-performance Bus (AHB). Advanced System Bus (ASB). Advanced Peripheral Bus (APB). CoreConnect: created by IBM Supports 32, 64 and 128-bit data bus, extendable to 256 bits. Includes the next elements: Procesor Local Bus (PLB). On-chip Peripeheral Bus (OPB). A bus bridge. DCR bus. * Figure extracted from [12]. IP Cores in the market ALTERA: Altera MegaCore functions and AMPP Megafunctions Embedded processor cores supported by SOPC Builder NIOS, NIOS II, several 16, 8, 4-bit microcontrollers. Interfaces and peripherals SRAM memories, interrupt controllers, UARTs, USB, I2C, DMA controllers, PCI, PCI-X buses, Ethernet controllers, LCD and smart card interfaces, etc. Communications standard-based communication protocols and interfaces such as UTOPIA, HDLC, Bluetooth, FlexBus, and others. DSP supported by DSP Builder tool • Filtering and modulation: FIR, IIR filters, Up-converters, NCOs. • Transforms: FFT, IFFT, DCT and DWT. • Error correction: Reed Solomon encoder/decoder, Viterbi encoder/decoder • Image and Video processing: color space converter, JPEG and JPEG2000 encoder/decoder. IP Cores in the market DSP core Category Vendor DSP core Category Vendor FIR Compiler 3.3.0 Filtering Altera Complex Tuner Audio AMPP partner Digital Modulator Modulation/Demodulation AMPP partner ADPCM Encoder/Decoder Audio AMPP partner Up Converter Modulation/Demodulation AMPP partner Floating Point Arithmetic Unit Arithmetic AMPP partner Arithmetic AMPP partner FFT/IFFT 2.2.0 Transforms Altera Floating Point Pipelined Divider Unit 2D DCT/IDCT Transforms AMPP partner NCO Compiler 2.3.0 Signal Generation Altera 2D DWT Transforms AMPP partner Telephony Gain Generation Signal Generation AMPP partner 64-point FFT/IFFT Transforms AMPP partner Telephony Tone Generation Signal Generation AMPP partner DCT Transforms AMPP partner Digital IF Receiver Others AMPP partner Correlation Correlation Altera Digital PLL Synthesizer Others AMPP partner Reed Solomon Compiler, Encoder 4.0.1 Error Correction Altera Dual Resampler 1Y and 4Y Others AMPP partner Reed Solomon Compiler, Decoder 4.0.1 Error Correction Altera Accelerated Display Graphics Engine Others AMPP partner Viterbi Compiler, High-Speed Parallel Decoder Error Correction Altera Viterbi Compiler, Low-Speed/Hybrid Serial Decoder Error Correction Altera Turbo Product Coder Decoder Error Correction AMPP partner Color Space Converter 2.3.0 Video & Image Processing AMPP partner CCIR-656 Decoder Video & Image Processing AMPP partner CCIR-656 Encoder Video & Image Processing AMPP partner JPEG Encoder Video & Image Processing AMPP partner JPEG Decoder Video & Image Processing AMPP partner JPEG2000 Encoder Video & Image Processing AMPP partner JPEG2000 Decoder Video & Image Processing AMPP partner MPEG2 Decoder Video & Image Processing AMPP partner Altera MegaCores and AMPP Megafunctions for DSP IP Cores in the market XILINX: Xilinx LogicCORE functions and AllianceCORE IP cores Similar IP alternatives in interface / peripherals and Communications. Embedded processor cores supported by Platform Studio PicoBlaze, MicroBlaze, 16, 8, 4-bit microcontrollers. DSP supported by System Generator for DSP tool DSP core Category Support Vendor 16-bit RISC Digital Signal processor PDSP core Xilinx #1 IP-cores 16-bit TMS320C25 DSP core PDSP core Altera, Xilinx Cast Inc. 16-bit TMS32025 DSP core PDSP core Xilinx Cast Inc. DSP56002 24-bit DSP core PDSP core Xilinx Cast Inc. Soft processor cores PDSP soft cores Soft processor core Architecture Interface CoreMP7 32-bit ARM-based RISC architecture AMBA (AHB) bus interface NIOS II 32-bit RISC architecture AMBA (AHB) bus interface NIOS 16/32-bit RISC architecture MicroBlaze 32-bit Risc architecture PicoBlaze 8-bit microcontroller N/A CoreConnect (OPB) standard N/A Additional DSP features -Hardware multiply, hardware divide and barrel shifter -Hardware multiply, divide, barrel shifter, single-precision floating-point unit -- Vendor Actel Altera Altera Xilinx Xilinx Example with FIR Filter Compiler Create a new project and open the MegaWizard Plug-In Manager Example with FIR Filter Compiler Create a new Megafunction unit and select FIR Compiler 3.3.0 from the IP MegaStore Example with FIR Filter Compiler Options in the IP Toolbench: Example with FIR Filter Compiler 1.- Parameterize step: New/edit coefficient set Plot options: fixed / floating coefficients, frequency response / time response and coefficients Coefficients bitwidth: 2 to 32 Coefficient scaling Device family Filter structure: fully-serial, fully parallel, multi-bit serial (DA) Pipeline level Data/coefficient storage: logic cells, memory blocks Output/ Input specifications Example with FIR Filter Compiler Coefficient generator: Rate: single, interpolation, decimation Filter type: low-pass, high-pass, band-pass, band reject. Number of coeficients. Cutoff freq. Sample rate. Window type: rectangular, Hamming, Hanning, Blackman Example with FIR Filter Compiler Example with FIR Filter Compiler 2.- Simulation Step: •Simulation model: VHDL and Verilog •Quartus II •Matlab M-file generation 3.- Generation Step Example with FIR Filter Compiler Instantiation Compilation results: Example with FIR Filter Compiler Simulation results: References [1] International Technology Roadmap for Semiconductors (ITRS), 2001. [2] “Hard Macros will revolutionize SoC Design”, E. Wein, EE Design, 2004. [3] Virtual Socket Interface Alliance (VSIA), website: www.vsi.org [4] Open Core Protocol International Partnership (OCP-IP), website: www.ocpip.org [5] The Structure for Packaging, Integrating and Re-using IP within Tool-flows (Spirit) Consortium, website: www.spiritconsortium.com [6] Altera Corporation, website: www.altera.com [7] Xilinx Corporation, website: www.xilinx.com [8] Lattice Semiconductor Corporation, website: www.latticesemi.com [9] QuickLogic Corporation, website: www.quicklogic.com [10] OpenCores Project, website: www.opencores.com [11] AMBA Home Page, website: www.arm.com/products/solutions/AMBAHomePage.html [12] CoreConnect Home Page, website: www-03.ibm.com/chips/products/coreconnect/