Transcript Advanced Digital Design - Vienna University of Technology

Advanced Digital Design
Asynchronous EDA
by A. Steininger, J. Lechner and R. Najvirt
Vienna University of Technology
Overview
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Synchronous-Asynchronous Direct
Translation (SADT)
Null Convention Logic
Syntax Directed Compilation (Balsa)
Martin Synthesis (Caltech
Asynchronous Synthesis Tools)
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner & R. Najvirt / TU Vienna
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Synchronous-Asynchronous
Direct Translation (SADT)
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Starting point: synchronous circuit
description in a standard HDL
Synthesis with conventional tools into
sync. gate-level netlist
Transformation of synchronous netlist
into asynchronous netlist
Technology mapping
Place and Route
Timing Verification
Lecture "Advanced Digital Design"
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De-synchronization
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SADT approach
Design style: Bundled data
Substitution of flip-flops by latches
Substitution of clock by local
asynchronous controllers
De-synchronized circuits ...
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never halt (liveness)
perform same computations as
synchronous circuit (flow-equivalence)
Lecture "Advanced Digital Design"
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De-synchronization
Conversion steps
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Conversion of Flip-flops to latches
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Generation of delays elements for
request signals
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D-FF separated into master/slave latches
matched to length of critical path of
combinational logic
Implementation and wiring of
asynchronous latch controllers
Lecture "Advanced Digital Design"
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De-synchronization
Circuit Architecture
Synchronous circuit
De-synchronized circuit
[Cortadella et al., 06]
Lecture "Advanced Digital Design"
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De-synchronization
Asynchronous Controllers
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Controller for master/slave latches
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Different controller implementations
with more or less concurrency possible
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4-phase protocol
Non-overlapping
Semi-decoupled 4-phase
Fully-decoupled 4-phase
De-synchronization control
More concurrency => fast pipeline
More concurrency => larger controllers
Lecture "Advanced Digital Design"
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De-synchronization
Flow Equivalence
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Definition: Two circuits are flowequivalent if they ...
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have the same set of latches
For each latch, the sequence of stored
values is the same in both circuits
[Cortadella et al., 06]
Lecture "Advanced Digital Design"
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De-synchronization
Pros/Cons
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Advantages
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Use of standard HDLs
Use of industrial-strength synthesis tools
Almost no re-education for hardware
designers necessary
Simple porting of legacy designs
Negligible area overhead compared to
synchronous implementation
Disadvantages
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1-to-1 mapping of sync. circuits can lead to
sub-optimal designs
Lecture "Advanced Digital Design"
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Click Elements
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Published as an implementation style
for data-driven compilation (Haste)
Also useful for implementing
asynchronous equivalents of
synchronous circuits
Uses flip-flops for storage
Most elements implementable with
cells from a standard (sync) library
Arbiter still required (not for SADT)
Lecture "Advanced Digital Design"
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Click Elements
Lecture "Advanced Digital Design"
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Null Convention Logic
Synthesis
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RTL Synthesis
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Transform VHDL/Verilog to 3NCL netlist
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Off-the-shelf synthesis tools
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Netlist contains just AND & INV gates
NULL values are treated as “don’t care”
Logic optimizations
Dual-rail expansion
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3NCL netlist to 2NCL netlist
DIMS implementation of AND & INV gates
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Produces a delay-insenstive circuit
Logic optimizations
Lecture "Advanced Digital Design"
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Dual Rail NAND
DIMS implementation
Lecture "Advanced Digital Design"
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[Ligthart et al.,
2000]
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Null Convention Logic
Technology Mapping
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DIMS implementation inefficient
Techn. mapping on threshold gates
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Circuit functionality fully described by set
function of DIMS implementation
DIMS smoothing: Derive boolean network
representing set function
Threshold gates have specific set function
Perform logic optimization and map
boolean network to available threshold
gates
Lecture "Advanced Digital Design"
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Dual Rail NAND
[Ligthart et al.,
2000]
DIMS implementation
Lecture "Advanced Digital Design"
Set function
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Null Convention Logic
Threshold Gates
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Library of threshold gates by Theseus
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all unate functions with up to 4 inputs
Lecture "Advanced Digital Design"
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Syntax-Directed Compilation
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1-to-1 mapping of language
constructs to handshake circuit
components
Uses a library of highly optimized
standard cell components for simpler
physical synthesis and verification
Allows experienced designer to easily
envision the resulting circuit but limits
optimization potential
Lecture "Advanced Digital Design"
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Balsa
Handshake Circuits
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Approx. 40 handshake components
Connected over channels
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Push channel
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Data path associated
Pure control channels (no data transferred)
Active ports initiate communication
Passive ports respond to request
Data flow from active to passive port
Pull channel
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Data flow from passive to active port
Lecture "Advanced Digital Design"
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Example: Handshake
Components
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Fetch ()
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Transfers data upon request
Case (@)
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Conditional control flow element
Source: [Balsa Manual]
Lecture "Advanced Digital Design"
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Example:
Modulo-10 Counter
import [balsa.types.basic]
type C_size is nibble
constant max_count = 9
procedure count10(sync aclk; output count: C_size) is
variable count_reg : C_size
variable tmp : C_size
begin
loop
sync aclk;
if count_reg /= max_count then
tmp := (count_reg + 1 as C_size)
else
tmp := 0
end || count <- count_reg ;
count_reg := tmp
end -- loop
end -- begin
Lecture "Advanced Digital Design"
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Example:
Modulo-10 Counter
Source: [Balsa Manual]
Lecture "Advanced Digital Design"
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Martin synthesis
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The so-called Martin synthesis process
is seminal work of the async group
around A. J. Martin at Caltech
Design entry is CHP, result is PRS
Performs several transformations with
designer modifiable intermediate steps
Lecture "Advanced Digital Design"
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Process Decomposition
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First transformation
Reduces processes with complex
control structures to simple concurrent
subprocesses
Either syntax-directed (SDD) or datadriven (DDD)
Lecture "Advanced Digital Design"
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Syntax Directed Decomposition
Rule: A process P with construct S can be
replaced with processes P1, P2 and a new
channel C by replacing S with the
communication C and creating P2 of the
form *[[#C -> S; C]]
E.g. P: *[A; *[B1 -> S1 [] B2 -> S2]; B]
P1: *[A; C; B]
P2: *[[#C & B1 -> S1
[]#C & B2 -> S2
[]#C & ~B1 & ~B2 -> C]]
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner & R. Najvirt / TU Vienna
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Data Driven Decomposition
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More fine-grained than SDD
At the end, clustering can be
performed to merge subprocesses
again for better performance
First transformation to dynamic single
assignment (DSA) form:
Each variable can be written only once in
each main loop iteration, e.g.:
*[A?a; X!a; B?a; Y!a]
*[A?a1; X!a1; B?a2; Y!a2]
Lecture "Advanced Digital Design"
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Data Driven Decomposition (2)
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Second transformation is projection
First, transformations to allow projection
e.g. variable duplication and channel
addition:
*[A?a; x := a, y := ~a; X!x, Y!y]
*[A?a; a1 := a, a2 := a; x := a1, y := ~a2; X!x, Y!y]
*[A?a; {Ax!a, Ax?a1}, {Ay!a, Ay?a2};
x := a1, y := ~a2; X!x, Y!y]
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Then projection to some sets of
assignments
Sets: {A?, a, Ax!, Ay!} {Ax?, a1, x, X!} {Ay?, a2, y, Y!}
Projection: *[A?a; Ax!a, Ay!a],
*[Ax?a1; x := a1; X!x], *[Ay?a2; y := ~a2; Y!y]
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner & R. Najvirt / TU Vienna
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Handshake Expansion (HSE)
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Each communication channel is
replaced by handshake signals, e.g.:
*[…; C; …], *[#C -> …; C]
is transformed to (4-phase handshake)
*[…; r := 1; [a]; r := 0; [~a]; …],
*[r -> …; a := 1; [~r]; a := 0]
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Reshuffling can then be used to
increase concurrency/performance
(different handshake controllers)
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner & R. Najvirt / TU Vienna
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Production Rule Expansion (PRE)
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Transforms HSE to PR in three steps:
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State variable insertion
PR generation
Symmetrisation
Sequencing must be implemented
explicitly
*[[Lr]; Rr := 1; [Ra]; Rr := 0; [~Ra];
La := 1; [~Lr]; La := 0]
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner & R. Najvirt / TU Vienna
Lr
Ra
~Ra
~Lr
->
->
->
->
Rr+
RrLa+
La-
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Production Rule Expansion (PRE)
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Transforms HSE to PR in three steps:
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State variable insertion
PR generation
Symmetrisation
Sequencing must be implemented
explicitly
*[[Lr]; Rr := 1; [Ra]; Rr := 0; [~Ra];
~x & Lr
La := 1; [~Lr]; La := 0]
Ra
*[[Lr]; Rr := 1; [Ra]; x := 1; [x];
x
Rr := 0; [~Ra]; La := 1; [~Lr];
x & ~Ra
x := 0; [~x]; La := 0]
~Lr
~x
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner & R. Najvirt / TU Vienna
->
->
->
->
->
->
Rr+
x+
RrLa+
xLa-
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Production Rule Expansion (PRE)
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Transforms HSE to PR in three steps:
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State variable insertion
PR generation
Symmetrisation
Sequencing must be implemented
explicitly
*[[Lr]; Rr := 1; [Ra]; Rr := 0; [~Ra];
~x & Lr
La := 1; [~Lr]; La := 0]
Ra
*[[Lr]; Rr := 1; [Ra]; x := 1; [x];
~Lr | x
Rr := 0; [~Ra]; La := 1; [~Lr];
x & ~Ra
x := 0; [~x]; La := 0]
~Lr
Ra | ~x
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner & R. Najvirt / TU Vienna
->
->
->
->
->
->
Rr+
x+
RrLa+
xLa-
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Summary
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Synchronous-Asynchronous Direct
Translation
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Synthesis with standard tools
Syncronous-Asynchronous transformation
Martin Synthesis
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Process decomposition
Handshake expansion
Production rule expanstion
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner & R. Najvirt / TU Vienna
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References
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Jordi Cortadella, Alex Kondratyev, Luciano Lavagno,
Christos P. Sotiriou. Desynchronization: Synthesis
of Asynchronous Circuits From Synchronous
Specifications. 2006
Alain J. Martin. Programming in VLSI: From
Communicating Processes to Self-timed VLSI
Circuits. 1987
Catherine G. Wong and Alain J. Martin. High-Level
Synthesis of Asynchronous Systems by DataDriven Decomposition. 2003
Ad Peeters, Frank te Beest, Mark de Wit, Willem
Mallon. Click Elements – An Implementation
Style for Data-Driven Compilation. 2010
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner & R. Najvirt / TU Vienna
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