Transcript Advanced Digital Design - Vienna University of Technology

Advanced Digital Design
Static Data-flow Structures
by A. Steininger and J. Lechner
Vienna University of Technology
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Outline


Recap: Handshake Protocols
Data-flow Abstraction





from handshakes to tokens
latches & pipelines
flow control elements
function blocks
Implementation
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
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recall
Asynchronous Circuits
request
SRC
f(x)
SNK
acknowledge
local handshake protocol
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
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Handshake Protocols
recall

Handshake style
4-phase / Return-To-Zero
 2-phase / Non-Return-To-Zero


Timing model
Bundled data
 Delay-Insensitive

Choice of protocol affects speed,
area, power
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Comparing the Styles
recall
handshake style
data
coding
single rail
multirail
signaling
4-phase
2-phase
(RTZ)
(NRZ)
bundled data
NCL
LEDR
level
transition
single rail
multirail
delay model
bounded
QDI
ACK
explicit handshake
REQ
explicit
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Lecture"Advanced
"Advanced
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compl. det.
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Data-flow Abstraction

Asynchronous data-flow circuits
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components communicate via channels
channels may implement any
protocol/coding
Building blocks (components):



Latches
Flow control elements:
Join, Fork, Merge, MUX, DEMUX
Functional blocks
RTL-like modeling of asyn. circuits
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Latches – The Concept

the ONLY components with active
part in handshaking:
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
process requests from „upstream“
latches => overwrite old data
issue requests to „downstream“ latches
=> provide new data
Abstraction: Tokens and Bubbles
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
Tokens: new data to be captured,
move downstream
Bubbles: „old“ data to be overwritten,
move upstream
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Latches - Symbols
Tokens marked with circles
 E.g., 4-phase protocol

E … empty codeword (NULL)
V … value codeword (DATA)
Token
Bubble
Token
Bubble
E
E
V
V
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Latches – Switching Rule
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Latch L1 may store data iff:
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all direct successor latches
(downstream) have consumed
(stored and acknowledged) L1‘s
current value
L1 thus stores a bubble

all direct predecessor latches
(upstream) provide new data
L1‘s predecessor(s) store a token
then the token moves on to L1
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Latches – Pipelines
L
a
t
c
h
f(x)
L
a
t
c
h
f(x)
L
a
t
c
h
f(x)
L
a
t
c
h
Token
Token
Bubble
Token
V
E
V
V
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Elastic Pipeline
recall
RIN
C
C
AOUT
C
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ROUT
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Elastic Pipeline
initial state
RIN
C
C
AOUT
ROUT
C
E
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E
E
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Elastic Pipeline
request (rising edge) / token
RIN
C
C
AOUT
ROUT
C
V
E
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E
E
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Elastic Pipeline
request/token passes stage 1
RIN
C
C
AOUT
ROUT
C
V
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E
E
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Elastic Pipeline
request/token passes stage 2
RIN
C
C
AOUT
ROUT
C
V
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V
E
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Elastic Pipeline
request/token passes stage 3 => output
RIN
C
C
AOUT
ROUT
C
V
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V
V
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Elastic Pipeline
further request/token
RIN
C
C
AOUT
ROUT
C
E
V
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V
V
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Elastic Pipeline
new request/token passes stage 1
RIN
C
C
AOUT
ROUT
C
E
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V
V
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Elastic Pipeline
new request/token passes stage 2
RIN
C
C
AOUT
ROUT
C
E
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E
V
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Elastic Pipeline
new request/token blocked for stage 3
RIN
C
C
AOUT
ROUT
C
E
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E
V
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Elastic Pipeline
one more request/token …
RIN
C
C
AOUT
ROUT
C
V
E
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E
V
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Elastic Pipeline
… passes stage 1 only
RIN
C
C
AOUT
ROUT
C
V
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E
V
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Elastic Pipeline
ACK consumes the rightmost token
RIN
C
C
AOUT
ROUT
C
V
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E
V
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V
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Elastic Pipeline
bubble moves upstream …
RIN
C
C
AOUT
ROUT
C
V
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E
E
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Elastic Pipeline
… up to stage 1
RIN
C
C
AOUT
ROUT
C
V
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V
E
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Pipeline - Rings
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Cycles for iterative computations
Initialization of registers:
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At least one bubble
At least one value and one empty token
Wrong initialization causes a deadlock
V
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V
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Control Flow Elements
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Transparent for handshaking
Unconditional: Join, Fork, Merge
Conditional: MUX, DEMUX
Join
Fork
MUX
DEMUX
MERGE
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Control Flow - Join
Join synchronizes inputs
 Requests are passed on when
all inputs are available

Missing input
All inputs ready
V
E
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V
E
V
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Control Flow - Join
Join synchronizes inputs
 Requests are passed on when
all inputs are available

Missing input
All inputs ready
V
V
E
Join blocks execution
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Tokens passed on
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Control Flow - Fork

Requests are passed on to
multiple successor stages
E
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V
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Control Flow - Fork

Requests are passed on to
multiple successor stages
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E
V
E
V
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Control Flow - Merge
Passes input tokens to output
 Mutually exclusive inputs!
 Full handshake routine needs to
be performed

0
1
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Control Flow - Merge
Passes input tokens to output
 Mutually exclusive inputs!
 Full handshake routine needs to
be performed

Token arrives at
input 0
V
0
1
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Control Flow - Merge
Passes input tokens to output
 Mutually exclusive inputs!
 Full handshake routine needs to
be performed

Value token is
passed on
0
1
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V
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Control Flow - Merge
Passes input tokens to output
 Mutually exclusive inputs!
 Full handshake routine needs to
be performed

0
1
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Value token is
consumed, receiver
sends ack and
demands empty
token
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Control Flow - Merge
Passes input tokens to output
 Mutually exclusive inputs!
 Full handshake routine needs to
be performed

Empty token arrives
E
0
1
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Control Flow - Merge
Passes input tokens to output
 Mutually exclusive inputs!
 Full handshake routine needs to
be performed

Empty token is
forwarded
0
1
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E
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Control Flow - MUX
Passes selected input to output
 The complete handshake routine
needs to be performed before
another input can be selected

0
1
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Control Flow - MUX
Passes selected input to output
 The complete handshake routine
needs to be performed before
another input can be selected

0
Input 0 is selected
V
0
1
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Control Flow - MUX
Passes selected input to output
 The complete handshake routine
needs to be performed before
another input can be selected

Value token is
passed on
0
1
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V
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Control Flow - MUX
Passes selected input to output
 The complete handshake routine
needs to be performed before
another input can be selected

0
1
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
Value token is
consumed, receiver
sends ack and
demands empty
tokens
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Control Flow - MUX
Passes selected input to output
 The complete handshake routine
needs to be performed before
another input can be selected

E
Empty tokens arrive
E
0
1
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Control Flow - MUX
Passes selected input to output
 The complete handshake routine
needs to be performed before
another input can be selected

Empty token is
forwarded
0
1
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E
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Control Flow - DEMUX
Passes input to selected output
 The complete handshake routine
needs to be performed before
another output can be selected

0
1
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Control Flow - DEMUX
Passes input to selected output
 The complete handshake routine
needs to be performed before
another output can be selected

0
Output 0 is selected
V
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0
1
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Control Flow - DEMUX
Passes input to selected output
 The complete handshake routine
needs to be performed before
another output can be selected

Value token is
passed on to output 0
0
V
1
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Control Flow - DEMUX
Passes input to selected output
 The complete handshake routine
needs to be performed before
another output can be selected

0
1
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
Value token is
consumed, receiver
sends ack and
demands empty
tokens
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Control Flow - DEMUX
Passes input to selected output
 The complete handshake routine
needs to be performed before
another output can be selected

E
Empty tokens arrive
E
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0
1
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Control Flow - DEMUX
Passes input to selected output
 The complete handshake routine
needs to be performed before
another output can be selected

Empty token is
transferred to output 0
0
E
1
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Functional Blocks

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Combinational logic
Perform computation
1.
2.
3.
Block waits for tokens on inputs
Performs function
Issues output tokens containing the
results
Implicit Join/Fork
Explicit Join/Fork
F
F
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Functional Blocks
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Transparent for handshaking
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Relay handshaking signals unmodified
For every input request exactly one
request must be produced at output
Ack
F
Data
Data
The function block is transparent for the
latches in terms of handshaking
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Functional Blocks
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
Strongly indicating: function block
waits for tokens on all inputs
before producing output tokens
Worst-case latency: slowest input
determines speed
Weakly indicating: function block
may produce some output tokens
as soon as they can be computed
(based on some subset of inputs)
Actual-case latency
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Implementation
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
Many different implementation styles
Implementation depends on used
handshake protocol
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Different area complexity



4-phase/2-phase
Bundled data/DI encoding
4-phase ≤ 2-phase
Bundled data ≤ DI encoding
Protocols may be mixed

Optimization of performance/area/power
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Implementation

Function blocks


Example: Full adder
Control Flow
MUX
 DEMUX
 Fork
 Join

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Adder -Bundled Data
Single rail implementation
 Matched delay

E.g., inverter chain
 Asymmetric delays for 4-phase

Ack
Req
a
b
cin
Lecture "Advanced Digital Design"
Matched Delay
Full Adder
© A. Steininger & J. Lechner / TU Vienna
sum
cout
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Adder – Dual Rail I

Delay-insensitive Minterm Synthesis (DIMS)


For dual-rail 4-phase functions
DNF built with Muller C-gates
a
b
cin
sum
cout
F
F
F
F
F
F
F
T
T
F
F
T
F
T
F
F
T
T
F
T
T
F
F
T
F
T
F
T
F
T
T
T
F
F
T
T
T
T
T
T
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
Source: [Sparso 06]
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Adder – Dual Rail II

NCL threshold gates with hysteresis
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
Proposed by Theseus Logic, Inc.
High when m-of-n inputs high
Low when all inputs low
Source:
[Sparso 06]
Lecture "Advanced Digital Design"
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Join - Bundled Data
4-phase join
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Source: [Sparso 06]
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Fork - Bundled Data
4-phase fork
Lecture "Advanced Digital Design"
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Source: [Sparso 06]
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Join - Dual Rail
4-phase join
Lecture "Advanced Digital Design"
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Source: [Sparso 06]
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Fork - Dual Rail
4-phase fork
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Source: [Sparso 06]
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MUX - Bundled Data
0
4-phase MUX
Source: [Sparso 06]
1
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DEMUX - Bundled Data
0
4-phase DEMUX
Source: [Sparso 06]
1
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