Transcript Organization - Vienna University of Technology

Advanced Digital Design
Organisation
A. Steininger / TU Wien
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„Key Data“
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Elective Subject Master CE
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Elective Subject PhD course
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Type: VU 6.0 SWS (6 ETCS)
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Lecturers
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Andreas Steininger
Robert Najvirt
Thomas Polzer
A. Steininger / TU Wien
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Course Context
Bachelor
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Digital Design VO
Digital Design & Comp Arch. LU
Hardware-Modelling
4.
5.
5.
Master
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HW/SW-Codesign
Advanced Digital Design
ES (Scientific) Project
Informatikpraktikum
Master Thesis
A. Steininger / TU Wien
WT
WT
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Course Aims
Provide you the competence to…
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deal with difficult (timing) issues in digital
design (esp. clock domain crossing),
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know about alternatives to the synchronous
design style,
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make the appropriate choice for a given
problem,
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practically apply the chosen style, and
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understand the involved limitations.
A. Steininger / TU Wien
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Course Contents
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Why a Design Style?
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Metastability:
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phenomenon, effects, MTBU-model, measurement
mitigation & synchronizers
GALS
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fundamental problem & generic timing model
hazards & glitches
data exchange via synchronizer / FIFO / pausible clock
Muller C-Element, MUTEX, Arbiter
Asynchronous Design
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Methods: Bundled Data & QDI
Data Flow & Control Structures („Token Game“, STG)
Design Entry & Design Automation
A. Steininger / TU Wien
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Course Structure
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Lecture (25%):
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Homeworks / Exercises (25%):
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standard lectures
10 units, 3 topical blocks
submission of written elaboration
discussion in the group, 3 units
Design Projects (50%)
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submission of solution
discussion with advisor / group
A. Steininger / TU Wien
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Homeworks/Exercises
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typically 3-5 problems assigned
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solutions to be worked out individually
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submission of pdf with solution
(minimum level of optical
attractiveness applies)
upload in MyTI
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submission no later than the day
before the discussion, 12:00 noon
A. Steininger / TU Wien
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Design Problems
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typically 3 problems assigned
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solutions to be worked out
in groups of 3
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submission of presentation slides with
solution; upload in MyTI
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submission no later than the day
before the discussion, 12:00 noon
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demo of working solution, until 1 week
after discussion, dates by appointment
A. Steininger / TU Wien
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Time & Location
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lecture:
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home exercise:
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every Wed 9 – 11 SemTI
2 weeks time for preparation
discussion on 3 selected lecture dates
design problem:
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free access to lab for experiments
discussion in 3 extra slots at 1-3pm:
on Nov 19, Dec 10, Jan 21
A. Steininger / TU Wien
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Course Material
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Lecture Slides
Homework Problems
Design Problems
Collection of Solutions
Textbooks
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web
web
web
web ?
Jens Sparso and Steve Furber
web (free)
Principles of Asynchronous Circuit
Design – A Systems Perspective
Kluwer
http://www2.imm.dtu.dk/~jsp/
David Kinniment
Synchronization and Arbitration
in Digital Systems
Wiley
A. Steininger / TU Wien
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Grading
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quality of submitted homeworks (25%)
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quality of submitted designs (35%)
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written examination (Jan/Feb) (40%)
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contributions
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during the lectures
during the discussions of homeworks
through presentation of own solutions
for each of the categories 40% of the achievable
points must be attained
A. Steininger / TU Wien
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