Transcript SRAM Generator - University of Virginia

SRAM Generator
- Satya Nalam
SRAM Architecture
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SRAM specs
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Single bank
Capacity – 8-32kb
Col-mux – 1,2,4,8
#Rows – 8-512
#Rows and #cols power
of 2
Timing block using
encounter
Schematic/Layout script
for tiling each block
Wrapper script to
generate final SRAM
Design
WLs
Pre-decode o/p
Enable
Address
Rd/Wr
BLs
BL PCH
CSEL
SAE
SAPCH
Col-muxed BLs
SA output
EN
Data in & out
Schematic Generation
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Can be completely automated
Parametrization
Use @key in Skill procedures for optional
arguments
Transistor sizes from optimization result
procedure(UvaEceSchematicCreateInstParNand2(cvid libName cellName Iname
location intop inbot out VDD VSS @key (lp 0.06) (wp 0.20) (ln 0.060) (wn 0.20) (m
1))
Schematic Generation
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Leaf-cell schematic creation
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Bitcells – PDK
Decoders – Skill
Everything else – Manual, can be replaced
by Skill
Layout Generation: WLD
WLD2
WLD1
WL Drivers
• Via-programmed
• Staggered for pitchmatching
Layout Generation: Array
Termination cells
Well taps
Layout Generation: Timing
Predecode outputs
Design placed and routed
by Encounter
Layout Generation: Bitslice
CD
SA
IO
IO Staggered for
pitch-matching
Layout Generation: Top-level
128x64
SRAM
Routing through Abutment - Fillers with metal
Summary of useful tips for
automation through Skill
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Using procedures – with @key optional
arguments
Via-programming
Staggering for pitch-matching
Routing through abutment
Final deliverable
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Completed set of highly parametrized
Skill scripts for SRAM schematic and
layout generation.
Technology and user independent.
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Class-specific work – parametrization of
schematic and layout scripts
Documentation in progress.