Transcript SRAM Generator - University of Virginia

SRAM Generator
-Satya Nalam
Motivation
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SRAM is an integral part of most SoCs
Goal: Automate SRAM design process
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Technology-independence
User-independence
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Overview
Project Scope
(Cadence SKILL)
Schematic script
SRAM schematic
leaf cells
SRAM Optimizer
Design
params
DESIGNER
leaf cells
Layout script
SRAM layout
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SRAM Architecture
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SRAM specs
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Single bank
Capacity – 8-32kb
Col-mux – 1,2,4,8
#Rows – 8-512
#Rows and #cols power
of 2
Timing block using
encounter
Schematic/Layout script
for tiling each block
Wrapper script to
generate final SRAM
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Programmable leaf-cell design
E.g. Vias programmed
in SKILL for
decoder/WL Driver
Sized by SRAM optimizier
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Routing by abutment
Leaf-cell 1
Leaf-cell 2
Routing taking
care of internal
to leaf cell
Signal between two leaf cells – E.g. WL between
WL Driver and Bitcell
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Example
Different column circuitry layouts generated
Default, Col-mux=1
Different SA
Col-mux=4
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Status
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Completed:
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To do:
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Full schematic-generation scripts
Leaf-cell layout scripts
Top-level layout script
Usage/Testing:
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Schematic generation (FreePDK)
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STT-RAM (Anurag)
Schematic + Layout generation (ST 65)
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BL-leakage cancelling SA (Sudhanshu)
Single-ended SA (Joe)
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Future work
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Automating leaf-cell layout design
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Tie optimizer with SRAM generator
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Py-cell approach
E.g. Write optimizer output to config
Reduce human intervention
Further improve user/technologyindependence
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