Transcript 6502_final

STT-RAM Generator
- Anurag Nigam
Motivation
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Challenges in SRAM
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Leakage current
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High Leakage
Solution
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Non-volatile memory
Memory Technology
Comparison
STT-RAM bit cell overview
BL
Hard Ferro magnetic layer
MTJ
Oxide layer
RP
RAP
WL
Free Ferro magnetic layer
MTJ
SL
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1 MTJ
1 access transistor
Bit-cell Design
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IMTJ = f (Vin, parameters)
Behavioral current source
Need to solve differential equation
How to solve differential equation ??
Capacitor current equation
V
I
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I = C dV/dt
C
V   I / Cdt
Bit-cell design
componentName = isource
I = f(V)
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Editing CDF parameter to create behavioral source
Bit-cell design
WL
BL=0V
SL=1V
Switching
Schematic
Write “1” Operation
Memory Interface
STT-RAM Macro
Data In
Data In
R/W
Write Driver
CLK
CLK
R/W
ADDR
Timing
Block
WLen
Data Out
Memory
Array
R’/W
ADDR
CL
WLS
Sensing Block
SAen
Data Out
Write Driver
TBUF
BL
TBUF
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Write “1”  BL =0 SL=1
Write “0”  BL=1 SL=0
SL
Sense amplifier design
Test bit-cell
R ()
R-V characteristic of MTJ
8000
7000
6000
5000
4000
3000
2000
1000
0
-1.5
RAP
RP
-1
-0.5
0
0.5
Applied Voltage (V)
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Two states (RAP and RP)
Resistance is a function of voltage
1
1.5
Schematic automation
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Leaf-cell schematic creation
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Bitcells – Manual (using current/voltage
sources)
Decoders – Skill
Sense amp. Timing block, Write driver –
Manual
Memory array creation
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1Kb array - Skill
Schematic automation
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Decoder
procedure(Create7to128DecoderSchematic(libname,cellname))
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Write Driver
procedure(CreateWriteDrSchematic(libname,cellname,C))
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Memory Array
procedure(CreateSTTRAMSchematic(libname,cellname,R,C))
1Kb STT-RAM array
128 x 8 array
Write Driver
Timing block
Sense amplifier
Read and Write operation
Write “1”
Read “1”
Write “0”
Read ”0”
clk
Data<0>
Out<0>
Deliverables
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STT-RAM bit-cell SPICE model
Skill script to generate complete
functional STT-RAM
Class-specific work
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Importing bit-cell model in ADE
Skill script development
Thanks for your time !