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Slide 0
TM
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
The Zen of
Nonvolatile
Memories
July 27, 2006
Paper 47.3
Erwin J. Prinz, Ph.D.
Device Engineer
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
TM
Acknowledgements
• Ko-Min Chang, Craig Swift
 NVM Device Engineering
• Thomas Jew, Ronnie Syzdek
 NVM Design
• Saied Tehrani, Jon Slaughter
 MRAM Technology
• Freescale TSO NVM Team
• Device, Process, Design, Reliability, Test
Slide 2
Outline
•
•
•
•
•
•
Slide 3
Introduction
Floating Gate Nonvolatile Memories
Nitride Charge Storage
Nanocrystal Charge Storage
Emerging NVM Concepts
Conclusions
Introduction
• Silicon Nonvolatile Memories (NVM) store
 Code
 Data
• Technology Driver for Scaling
 More bits shipped in 2006 than DRAM
• Rugged, secure, reliable
 Engine, transmission, …
Slide 4
Types of Nonvolatile Memories
Embedded Standalone Standalone
NVM (NOR)
NOR
NAND
Typical Application
Microcontroller
Cellular
Phone
MP3 Player,
Digital
Camera
Typical Density
(90nm technology)
1-32 Mb
256-512 Mb
2 Gb
Typical % of Chip
Area
5% - 50%
100%
100%
Bitcell Size (90nm)
0.18 µm2
0.09 µm2
0.05 µm2
20 ns
50-100 ns
15 µs
low
highest
high
Random Access
Read Time
Process Complexity
Slide 5
Nonvolatile Memory Moore’s Law
• Example: Engine & Transmission Controller
1982:
1990:
1998:
2000:
2003:
MC68HC11
MC68300
MPC555
MPC565
MPC5554
20k Devices
200k Devices 7M Devices
14M Devices
34M Devices
8-bit CPU
32-bit CPU
32-bit CPU
32-bit CPU
512 bytes
256 kB Flash 512 kB Flash
1.0 MB Flash
2.0 MB Flash
EEPROM
Slide 6
32-bit CPU
System on Chip with Emb. NVM
• Engine / Transmission
Controller
•
•
•
•
32-bit CPU Core
1 Mbit Embedded Flash
A/D Converter
Peripherals
• The Ultimate
System on a Chip
Freescale’s MPC565
PowerPCTM Microprocessor
Slide 7
System on Chip with Emb. NVM
• CPU – Bus – NVM
 LV / high speed
• Pad Ring
 I/O (2.5V or 3.3V)
• NVM Bitcells
VDD (Node) LV Transistors:
* High Speed Logic, CPU
* NVM Control Logic
 HV / statistics
• NVM Periphery
 Analog
• NVM HV Supplies
 Charge pumps
Slide 8
System on Chip with Emb. NVM
• CPU – Bus – NVM
 LV / high speed
• Pad Ring
 I/O (2.5V or 3.3V)
• NVM Bitcells
I/O Transistors (2.5V, 3.3V):
* Pad Ring
* NVM Module, Analog
 HV / statistics
• NVM Periphery
 Analog
• NVM HV Supplies
 Charge pumps
Slide 9
System on Chip with Emb. NVM
• CPU – Bus – NVM
 LV / high speed
• Pad Ring
 I/O (2.5V or 3.3V)
• NVM Bitcells
 HV write, statistics
Flash EEPROM Bitcells
* Dual poly, 1-transistor
* Added process cost
• NVM Periphery
 Analog
• NVM HV Supplies
 Charge pumps
Slide 10
System on Chip with Emb. NVM
• CPU – Bus – NVM
 LV / high speed
• Pad Ring
 I/O (2.5V or 3.3V)
• NVM Bitcells
 HV / statistics
~9V HV Transistors
* Needed for Write
* “Slow”
• NVM Periphery
 Analog
• NVM HV Supplies
 Charge pumps
Slide 11
System on Chip with Emb. NVM
• Many device types
 LV, I/O, HV, NVM
• Many design styles




Memory
Analog
HV Switch
Synthesized Logic
• Many Design Tools !!
Freescale’s MPC565
PowerPCTM Microprocessor
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 SoC design flow
 NVM Reliability
Modeling
 Bitcell Modeling
Traditional NVM Operation
oxide
nitride
G
G
S
oxide
G
FG
D
S
D
S
D
W
W
W
n-MOSFET
Floating Gate
NVM Bitcell
SONOS
NVM Bitcell
Slide 13
Floating Gate NVM Operation
0
S
9
-9
3.5
G
G
G
FG
W
0
5
9
D
S
Hot Electron
Injection
Write
Slide 14
FG
W
9
9
0
D
S
Fowler-Nordheim
Tunneling
Erase
FG
W
0
Read
0.5
D
NAND
NOR
Bit Line 1 Bit Line 2
Select Line 1
Word Line 1
Word Line 2
Word Line 31
Word Line 32
Select Line 2
Common Source
Slide 15
Word
Line 1
Word
Line 2
Bit Line 1
Bit Line 2
Floating Gate Scaling Limit
complete
charge
loss
oxide
defect
partial
charge
loss
oxide
defect
silicon nanocrystals
G
G
FG
S
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D
D
S
W
W
Floating Gate
NVM Bitcell
Nanocrystal
NVM Bitcell
High Reliability Aspect of NVM
• End-of Life Bitcell
Modeling
 Knowledge of failure
modes
• Interaction of Bitcell
with NVM Design
 Calibrated Tools
• Failure Rate Prediction
for SoC
• Zero Defects
Slide 17
1-Transistor vs. Split Gate Bitcell
G
Drain-Side
Hot Electron
Injection
FG
D
S
200µA
W
1-Transistor
Floating Gate
Bitcell
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“Source-Side”
Hot Electron
SG
Injection
CG
S
D
2µA
W
Nanocrystal
Split Gate
Bitcell
Limitation of High Read Voltage
• 1-Transistor Array
• Split Gate Array
READ
LEVEL
E
0V
Slide 19
READ
LEVEL
W
E
2.5V 3.5V 4.5V
-1V
W
0V
1.2V 2.2V
Nitride Charge Storage (SONOS)
oxide/nitride/oxide
G
Charge Packet for Bit 1
Bit 2
S
D
W
Slide 20
Virtual Ground Array
Source/Drain
Source/Drain Line 2 Source/Drain
Line 1
Line 3
Word Line 1
Word Line 2 Bit 1 Bit 2
Slide 21
Silicon Nanocrystal NVM
• 5-10 nm diameter
“nanocrystals”
Slide 22
Silicon Nanocrystal Formation
• Manufacturable in RT-CVD Tool
4nm
Slide 23
8nm
10nm
12nm
20nm
Novel Device Concepts …
silicon
nanocrystals
G
D
S
boron doping
W
Slide 24
S
G
D
phosphorus
doping
indium doping
W
… and Experimental Results
Threshold Voltage (V)
4
Boron Only
Indium + Phosphorus
3
2
1
0
0.12
0.15 0.18
0.21 0.24 0.27
Drawn Channel Length (µm)
Slide 25
Revolutionary Memory: MRAM
• Information stored as
magnetic polarization
• Detected as a
resistance
 RMIN or RMAX
• Isolation transistor can
be logic device, no high
on/off ratio needed
• Bit cell size competitive
with embedded DRAM
• 4 Mbit MRAM in
production now !
Slide 26
Other Novel Methods of NVM
• FeRAM
 Bitcell Scalability ?
• Phase Change Memory
 Data Retention at Elevated Temperatures ?
• Resistive RAM
 Device Understanding ?
Slide 27
Conclusions
• Floating gate NVM scalable to
65 nm or 45 nm
• SONOS, nanocrystal Flash to 32 nm
• Revolutionary, more universal memories
being developed
 Require killer application for deployment
• Challenges in design, verification, reliability,
test, manufacturing …
Slide 28