Transcript Slide 1

‫הפקולטה למדעי ההנדסה‬
Faculty of Engineering Sciences
Lecture Contents
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Introduction
SRAM Overview
Novel SRAM bitcell
Test Chip Architecture
Summary
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
Memory Classification
Memory is classified by 4 major categories
Volatility, Access Speed, Capacity and Cost
Introduction
6T SRAM
Bitcell Design
Volatile
Non Volatile
SRAM
DRAM
REGISTER
CACHE
FLASH
EEPROM
HARD DISK
Architecture
Summary
Motivation & Goal
• Minimum energy point in digital circuits is
achieved at subthreshold voltages
(Vdd < Vt).
• Low-voltage operation of SRAM memories
in the subthreshold region offers substantial
power and energy savings at the cost of
speed.
• This project focuses on the design and
implementation of a novel SRAM bitcell for
use in the subthreshold region.
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
SRAM OVERVIEW
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
Overview
Bistability Principle (Q, QB)
Differential Read (Sense Amp)
Fast Access Speeds (read, write)
Differential Write
Large Noise Margins
Large Area (6 transistors)
Prechargable Bitlines
Power Consuming
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
Bistability – Butterfly Curve
• Positive feedback creates two stable points “1” and “0”.
• Regenerative property ensures a noisy cell converges back to
nominal values.
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
SRAM – Read Access
1.
2.
3.
4.
Bitlines (BL, BL’) are precharged to VDD
Wordline signal (WL) is asserted
One of the bitlines is pulled down toward GND.
Differential signal (BL-BL’) is amplified to accelerate the
process.
WL
V DD
M4
BL
Q= 0
M5
V DD
M1
Q= 1
V DD
Cbit
Introduction
BL
M6
V DD
Cbit
6T SRAM
Bitcell Design
Architecture
Summary
SRAM – Write Access
1. Bitlines are precharged to complementary values.
2. Worldline signal (WL) is asserted.
3. Q is pulled down to GND while Q’ is driven to VDD.
WL
V DD
M4
M5
M6
Q= 0
Q= 1
M1
V DD
BL = 1
Introduction
6T SRAM
BL = 0
Bitcell Design
Architecture
Summary
SRAM – Subthreshold Challenges
• In general, ratioed digital circuits are more
likely to fail in subthreshold voltages.
• 6T Bitcells cannot operate below
600mV – 700mV.
• Read SNM problem - degraded read noise
margins decrease bitcell stability.
• Write fails under 600mV due to the increase
of the pMOS drive in sub-threshold.
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
NOVEL 9T SRAM BITCELL
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
The Research Work
• Numerous novel low-power SRAM memories
have been proposed in recent years.
• We studied and analyzed many of the important
proposals which include :
6T, 7T, 8T, 9T, 10T bitcells, Virtual VDD, Virtual
GND, DCVSL, Voltage Boost, Read Buffer, Read
Assist, Voltage Boost, and more …….
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
Brain Storming
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
Major Achievements
• Two innovative SRAM 9T bitcells, named PSRAM and
SFSRAM , aimed at eliminating static power consumption
and operated in the subthreshold region were fully
designed and analyzed.
• Three types of 8-kb 40 nm SRAM test chips, nicknamed
RAMBO, were designed for operation at 600mV and
below.
• We are the first academic research team in
Israel to fully design and fabricate a
state-of-the-art 40nm CMOS silicon chip.
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
Chip Design Workflow
MC
Functionality
Simulations
MC
Performance
Tests
MC
optimizations
Full Chip(8-kb
Array) Layout
Test Chip
Architecture
Design
MC layout
Post Layout
Simulations
TAPEOUT!
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
Standard 8T – Schematic and Layout
NWELL
WBL
RBL
WBLB
GND
WBL_
WBL
Schematic
Stick Diagram
of a of
standard
a standard
8T SRAM
8T SRAM
bitcell
bitcell
VDD
GND
PQ
PQ_
WWL
Q NQ WBLB
TQ TQB
WBL
QB
VVDD
Q
VVDD
TQ_
TQ
Q
Q
WWL
QB
GND
RWL
VDD
QB NFB
Q
PQ
RBL
NRB QB
Q
NQ
Q_ QB
VVDD
NQ_
NQB
QB
Q
PQB
QB
NFB
VDD
NRWL
QB
RWL
RWL NRWL
RBL
RB
WWL
RB
WWL_
Q
NRB
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
Pseudo SRAM (PSRAM)
Pseudo static behavior - A novel bitcell
mechanism disposes of both data node
charges while holding a logical “1”.
Leakage current is practically eliminated
during this low-power standby mode.
Up to 3.75X less static power consumption
than a standard 8T cell at 0.9V.
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
PSRAM – Write “1” Operation
CLK synchronizes write access
[V]
CLK
[V]
WWL
time(s)
[V]
Q,QB
time(s)
[V]
WBL, WBLB
time(s)
1.1
0.0
0.6
Write wordline (enable) is asserted
0.0
Q is driven to “1” and QB to “0”
Q is discharged to during standby
0.6
0.0
0.6
WBL is driven to “1” and WBLB to “0”
0
time(s)
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
PSRAM – Power Reduction
Data node
Holdvoltages
“1" Standby
“0"
at process
Powercorners
16.0
6.00
200
(Normalized)
Power
Leakage
(Normalized)
Power
Leakage
1.35X
12.0
150
3.75X
Q, QB [mV]
4.00
8.0 100
2.00
4.0
2.5X
50
0
SS
0.00
0.0
0.4 V
SF
0.5 V
FS
0.6 V
FF
0.7 V
TT
0.8 V
0.9 V
PSRAM Q T8 QB SFSRAM
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
SFSRAM (Supply Feedback SRAM)
Enables subthreshold write with a VirtualVDD technique – weakening the Supply VDD
during write operation.
A new approach for the design of the VirtualVDD scheme reduces periphery and thus,
reduces write power.
Operates at ultra-low voltages, down to
200mV.
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
Standard 8T – Revisited
NWELL
WBL
RBL
WBLB
GND
WBL_
WBL
Schematic
Stick Diagram
of a of
standard
a standard
8T SRAM
8T SRAM
bitcell
bitcell
VDD
GND
PQ
PQ_
WWL
Q NQ WBLB
TQ TQB
WBL
QB
VVDD
Q
VVDD
TQ_
TQ
Q
Q
WWL
QB
GND
RWL
VDD
QB NFB
Q
PQ
RBL
NRB QB
Q
NQ
Q_ QB
VVDD
NQ_
NQB
QB
Q
PQB
QB
NFB
VDD
NRWL
QB
RWL
RWL NRWL
RBL
RB
WWL
RB
WWL_
Q
NRB
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
SFSRAM – Power Reduction
Hold “1" Standby Power
16.0
Leakage Power (Normalized)
12.0
3.75X
8.0
2.5X
4.0
0.0
0.4 V
0.5 V
0.6 V
PSRAM
Introduction
6T SRAM
0.7 V
8T
0.8 V
0.9 V
SFSRAM
Bitcell Design
Architecture
Summary
40NM TEST CHIP
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
GND
CLK
VDD
WR2SRAM
RD2SRAM
DIN2SRAM[31:0]
RD
DIN[31:0]
CLK
DVDD
DVSS
CLK
DVDD
DVSS
SVDD
VDD
DVDD
SVDD
WR
GND
CLK
GND
CLK
CLK
DVDD
32 x Precharge + Write Driver Units
WBL[31:0]
WBLB[31:0]
32
WBL[31:0]
GND
SVDD
PC
32
WBLB[31:0]
PC
WWL[63:0]
WWL[63:0]
WWL[63:0]
WWL[63:0]
RWL[63:0]
RWL[63:0]
RWL[63:0]
256
RWL[63:0]
WWL [255:0]
256
RWL [255:0]
Level Shifting Wordline Drivers x256
WL [255:0]
256
DVSS
GND
CS
CS
CS2SRAM
RD
WL_out [255:0]
ADD_in[7:0]
7
Row Decoder (8 :256)
ADD2SRAM[7:0]
Block 0
SVDD
SVDD
SRAM Array
64x32
RBL[31:0]
RBL[31:0]
RBL[31:0]
RBL[31:0]
32
RBL[31:0]
32 x Sensing Unit + Level Shifter
DOUT[31:0]
CLK
DVDD
GND
SVDD
32
SRAM2DOUT[31:0]
PASS_FAIL
DOUT[31:0]
32
DOUT[31:0]
Introduction
6T SRAM
CLK
DVDD
DVSS
SVDD
Block 3
Block 2
Block 1
RD
WR
DATA[31:0]
32
ADD[7:0]
8
ADD[7:0]
BIST_CNTRL
BIST
WR
8-kb Array
Read-Bitline division
Level Shifters
Row Decoder
Sense-Amps
Precharge Units
Write Drivers
BIST
DIN[31:0]
32
CS
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CLK
DVDD
DVSS
Chip Architecture
Bitcell Design
Architecture
Summary
CLK
DVDD
DVSS
SVDD
40nm Test Chip - Periphery
RBL_1
SA
SVDD
GND
SVDD
GND
SA
RBL_0
DVDD
DATA OUT
DATA IN
SA
SVDD
SVDD
ENABLE
GND
RBL_4
SVDD
GND
SVDD
SA
GND
GND
ENABLE
GND
RBL_3
Schematic of Sensing Unit + Up Shifter
WBL_L
WBL_R
RD
CLK
WL Selected
SVDD
DVDD
SVDD
Schematic of Write Driver
DVDD
SVDD
GND
WR
RWL Selected
CLK
WWL Selected
WL Selected
Schematic of WL Driver + Down Shifter
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
2.90 um
1.40 mm
Test Chip Top Level Layout
1.40 mm
Introduction
6T SRAM
1.40 um
Bitcell Design
Architecture
Summary
Chip Timing Diagrams
CLK
ADDR
WR_DATA
WR
RD
Selected WL
Selected WWL
Selected RWL
Selected WBL
Selected WBLB
Selected RBL
RD_DATA
SRAM access is synchronized by a clock. Bitline Precharge, write driving and digital logic execute during the high phase
and read/write take place during the low phase.
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
SUMMARY
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
Summary
A fully functional 8-kb array was layed out
and designed for the 40nm lp TSMC process.
SFSRAM Memory successfully operates at
subthreshold voltages - no additional
periphery required.
Additional power savings can be achieved in
the PSRAM with a majority bit algorithm.
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
Summary – Continued
PSRAM consumes up to 3.75X less static
power than a standard 8T cell.
We Are The first academic research team in
Israel to fully design and fabricate a
state-of-the-art 40nm chip.
Introduction
6T SRAM
Bitcell Design
Architecture
Summary
Questions??
Chocolate Chip
Digital Chip
Introduction
6T SRAM
Bitcell Design
Architecture
Summary