Transcript 投影片1

Design Review
AVI1005 A1
Sean Wang
2010/10/21
Item
1.
2.
3.
4.
5.
6.
7.
8.
9.
Driver FET floor plans and layout sizes
Bias Circuit Analysis with Equation
Comparator Offset Analysis & Sensitivity to Tail Current
Condition to Cause Initial Latch Problem & Solutions
Hystersis Comparator to Replace Latch?
Chip simulation results (open-loop simulation)
Rbias, Raout Determine VDS (Derive Equation)
Loss of Power MOSFET
Meas System, in Particular Base Noise
1. Driver FET floor plans and layout sizes
Iso-Asy-NMOS
Asy-PMOS
1000 um
1000 um
820 um
780 um
Floor Plan
85um x 245um
Vcc
GATE
Pre-Driver
PGND
180um x 250um
2. Bias Circuit Analysis with Equation
I2 
VB VGS 1


R2
R2
Vt 
R2
2I1


Vt  Vvov
R2
VDD ,min  VGS 1  VGS 2  I1  R1
If VDD Variation
[VVDD  (VVDD 
VVDD

R2
VVDD
gmmn 2  R2
 gmmn1  R1 )] /( R1  gmmn1  R2 )
1  gmmn 2 R2
3.1 Comparator Offset Analysis & Sensitivity to Tail Current
IMPD1
IMPD2
VSP1
VOUT
VN
VP
Vth 
Avt
W  L M
offrdn  Vth pd 1, pd 2 
2
2
2
2
2
 g
  g m nc 2,nc 2  Vthnc 3,nc 4   g m pc1, pc 2  g mnc 1,mnc 2  Vth pc1, pc 2  
m nc1, nc 2  Vthnc1, nc 2
 
 
 
 
 
 
 

g m pd 1, pd 2
g
g

g
mpd 1, pd 2
mp 1, p 2
mnc 3, mnc 4
 
 
 

3.2 Comparator Offset Analysis & Sensitivity to Tail Current
IMPD1
IMPD2
VSP1
VOUT
VN
VP
T_Rise_ comp
T_Fall_ comp
ppg_r_comp
ppg_f_comp
ppg_r_totall
ppg_f_totall
Origin (nS)
6.87
6.94
56.98
126.70
282.40
106.20
Improve (nS)
6.52
5.49
49.09
18.20
145.10
119.80
4.1 Condition to Cause Initial Latch Problem & Solutions
Problem
A. 假如使用Latch的方式，則在上述情況下，會發生Initial Latch的情形
Rising time is too slow
4.2 Condition to Cause Initial Latch Problem & Solutions
Solution
A. 讓AOUT的Rising Time加快
B. 設計電源進來時產生Blanking Time，時間內不判斷Aout訊號，並導通POWERMOS
Use for improve rising time
High Side : PMOS
Use for Blanking
5. Hystersis Comparator to Replace Latch?
A. 考慮Drain電壓在DCM T3時會造成Ringing，使得AOUT = Vdrain x gm x Raout
AOUT變化過大，因此使用Hysister無法解決此現象
B. 可考慮使用Latch或Blanking的方式，解決此問題
6. Chip simulation results (open-loop simulation)
Zoon In
VDRAIN dc 0.1V
7.1 Rext, Rint Determine VDS (Derive Equation)
VB ,Q1  VCC  I E ,Q1 Rext
VCC  VB ,Q1
 I E ,Q1
Rext
I E ,Q1
I E ,Q 2

I E ,Q 2 
IS  e
VBC ,Q 1 / VT
IS  e
VBE ,Q 2 / VT
I E ,Q1  eVBE 2 / VT
VBC ,Q 1 / VT
e
VCC  VB ,Q1
VCC  VB ,Q1
e
VB ,Q1 / VT
I E ,Q 2 
Rext
V
e
VB ,Q1 / VT
/V
Rext
2
VCC 
 RINT
(VB ,Q1 VDR ) / VT
3
e
if VBE  VB ,Q 2  0.7v, VCC  12V, R  10k
e BC ,Q1 T
VC ,Q1  I out  Ron  VDR
VDR  8.97m v
I E ,Q 2 
VCC  VB ,Q1
e
VB ,Q1 / VT
Rext
eVB1 VDR / VT
8.1 Loss of Power MOSFET
8.2 Loss of Power MOSFET