Transcript Chapter 6
Chapter 6 (II) Designing Combinational Logic Circuits (II) •Dynamic CMOS Logic V1.0 5/4/2003 V1.1 5/11/2003 V1.2 5/15/2003 1 EE141 Combinational Circuits Revision Chronicle 5/4: Split Chapter 6 into two parts: Part I focuses on Static and Pass Transistor Logic. Part II focuses on Dynamic Logic 5/11: Make minor revision in figures and adding the summary. 5/11: Make minor revision in figures and equations 2 EE141 Combinational Circuits Dynamic CMOS In Static CMOS circuits, at every point in time (except when switching), the output is connected to either GND or VDD via a low resistance path. Fan-in of n requires 2n (n NMOS plus n PMOS) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. Requires on n + 2 (n+1 NMOS plus 1 PMOS) transistors 3 EE141 Combinational Circuits Basic Dynamic Gate Clk Clk Mp Mp Out In1 In2 In3 Clk Out CL PDN A PDN C B Me Clk Me 4 EE141 Combinational Circuits Two Phase Operations Clk Clk Mp Mp off on Out In1 In2 In3 Clk CL PDN 1 Out AB+C A C B Me Clk Precharge (Clk = 0) Evaluate (Clk = 1) off Me on Out CLK ( A B C) CLK 5 EE141 Combinational Circuits Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation (one chance only). Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during the evaluation phase (PDN off), state is stored on CL Different from Static CMOS Output is connected to Either Vdd or GND through low-resistance path. 6 EE141 Combinational Circuits Properties of Dynamic Gates (I) Logic function is implemented by the PDN only Number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (VOL = GND and VOH = VDD) Non-ratioed: Sizing of the devices does not affect the logic levels (c.f., Pseudo NMOS) Faster switching speeds Reduced load capacitance due to reduced Logical Effort (Cin) Reduced load capacitance due to smaller internal capacitance. No short-circuit current, Isc, so all the current provided by PDN goes into discharging CL 7 EE141 Combinational Circuits Properties of Dynamic Gates (II) Power Dissipation No static current path ever exists between VDD and GND (including Psc) No glitching Higher transition probabilities: Extra loading on CLK Overall power dissipation usually higher P than static CMOS 01 PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL are equal to VTn Low noise margin (NML) Needs a precharge/evaluate clock (CLK) tPLH = 0, tPHL = Function of CL and PDN 8 EE141 Combinational Circuits Charge Leakage (1) and (3): Reversed-biased diode (2) and (4): Subthreshold leakage current (dominated) 9 EE141 Combinational Circuits Charge Leakage •Need minimum clock rate up to a few kHz •Not good for low-performance applications such as watches, etc. 10 EE141 Combinational Circuits Solution to Charge Leakage •Adding Bleeder Transistor: Same approach as level restorer for pass-transistor logic. •The Bleeder transistor is made high (device is small) •A “feedback” configuration to elimaite static power consumption 11 EE141 Combinational Circuits Issues in Dynamic Design 2: Charge Sharing VDD Clk Mp Out CL A Ma X B0 Clk Mb Me Ca Cb •Charge stored originally on CL is redistributed (shared) over CL and CA •Lead to a drop on the output voltage •May cause incorrect output (e.g., the next stage is a Inverter gate). 12 EE141 Combinational Circuits Charge Sharing VDD Clk Mp case 1) if V out < VTn VDD Mp OutOut A CL C L AMa Ma X B=0 B0 Mb Clk Mb Me Initial: VOUT (t 0) VDD , VX (t 0) 0 X Ca Ca Cb Me (VX VDD VTn (VX )) C L VDD = C L Vout t + Ca VDD – V Tn V X or Ca V out = Vout t – V DD = – -------- V DD – V Tn V X C L (VOUT VX ) case 2) if V out > VTn C --------------------a - Vout = –V DD C + C a L Cb VTn CA CL VDD VTn ( when VOUT VTn ) 13 EE141 Combinational Circuits Example of Charge Sharing (I) Y A B C Va Vb Vc Vd 0 at time0 Worst case: ABC 30 2.5V 0.94V (30 50) 2.5 0.94 1.56V : Switching voltage of Inverter EE141 14 Combinational Circuits Example of Charge Sharing (II) C2 C7 low A0 low A15 high when clk 1 Q in C1 is dumped intoC 2 C 7 Q in C1 Vn1 C1 VDD 7 ( Ci ) C1 i 2 IF C1 3 C2 & C2 C3 C4 C5 C6 C7 t hen Vn1 3C2 VDD 0.33VDD 1.65V 6C2 3C2 T urn ont heinvert er!! 15 EE141 Combinational Circuits Solution to Charge Redistribution Clk Mp Mkp Clk Out A B Clk Me •Precharge critical internal nodes using a clock-driven transistor (at the cost of increased area and capacitance) •All internal nodes are charged to Vdd during precharge No charge sharing occurs. EE141 16 Combinational Circuits Issues in Dynamic Design 3: Backgate Coupling Clk Mp A=0 Out1 =1 CL1 Out2=0 CL2 In B=0 Clk Me Dynamic NAND2 Static NAND2 17 EE141 Combinational Circuits Backgate Coupling Effect Clock feedthrough 3 2 Out1 1 Clk 0 In Out2 2 Time, ns -1 0 4 6 Output of static NAND gate does not drop all the way down to GND with the degraded Out1 18 EE141 Combinational Circuits Issues in Dynamic Design 4: Clock Feedthrough Coupling between Out and Clk input of the precharge device due to the Clk Mp A CL gate-to-drain capacitance. The voltage of Out can rise above VDD. B Clk Out The fast rising (and falling edges) of Me the clock couple to Out. May cause Latch-up! 19 EE141 Combinational Circuits Cascading Dynamic Gates V Clk Mp Clk Mp Out1 Me Clk Out2 In In Clk Clk Me Out1 Out2 VTn V ??? t Only ONE 0 1 transition allowed at inputs during Evaluation Phase EE141 20 Combinational Circuits Domino Logic Clk In1 In2 In3 Clk Mp 11 10 PDN Me Out1 Combat leakage & Charge sharing! Clk Mp Mkp Out2 00 01 In4 In5 Clk PDN Me 21 EE141 Combinational Circuits Why the Name “Domino”? Clk Ini Inj Clk PDN Ini Inj PDN Ini Inj PDN Ini Inj PDN Like falling dominos! 22 EE141 Combinational Circuits Properties of Domino Logic Only non-inverting logic can be implemented! Very high speed tpHL=0. Inverter can be sized to match Fan-out. Input capacitance reduced – smaller logical effort 23 EE141 Combinational Circuits Restructuring Logic for Domino Circuits Use simple Boolean Transform such as DeMorgan’s Law! 24 EE141 Combinational Circuits Multiple-output Domino Circuits Function of O3 = (C+D) can be reused! 25 EE141 Combinational Circuits Compound Domino Logic uses Complex Static Gates at the Output (O1 O 2) O3 ABCDEF GH 26 EE141 Combinational Circuits Designing with Domino Logic VDD VDD VDD Clk Mp Clk Mp Out1 Mr Out2 In1 In2 In3 PDN PDN In4 Can be eliminated! Clk Me Clk Me Inputs = 0 during precharge 27 EE141 Combinational Circuits Footless Domino VDD Clk VDD Mp Clk Mp Out1 0 Clk 1 0 Outn 1 0 In2 0 Mp Out2 In1 1 VDD 1 0 In3 1 0 1 Inn 1 0 The first gate in the chain needs a foot switch Precharge is rippling – short-circuit current A solution is to delay the clock for each stage 28 EE141 Combinational Circuits Differential (Dual Rail) Domino off Mp Mkp Clk Out = AB 1 on Mkp 0 Clk Mp 1 A !A 0 Out = AB !B B Clk Me Solves the problem of non-inverting logic 29 EE141 Combinational Circuits np-CMOS Clk In1 In2 In3 Clk Mp 11 10 PDN Me Out1 Clk Me In4 In5 PUN 00 01 Clk Mp Out2 (to PDN) Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN 30 EE141 Combinational Circuits NORA Logic Clk In1 In2 In3 Clk Mp 11 10 Out1 PDN Clk Me In4 In5 PUN 00 01 Clk Me To other PDN’s WARNING: Very Sensitive to Noise! EE141 Mp Out2 (to PDN) To other PUN’s 31 Combinational Circuits Summary of Dynamic CMOS Dynamic circuits should be designed with care (watch out charge sharing, etc.) It has smaller footprint and higher speed, but may not be best for low-power designs. The current trend is towards an increased use of complementary static CMOS Design Automation Tools: Optimization at the logic level, rather at the circuit level. 32 EE141 Combinational Circuits