Transcript Why Johnny Can`t Code

Why Johnny Can’t Code
Preparing Engineers for Billion
Gate Designs
Mike Keating
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Interview Question
A
D
C
B
2x the
processes
= 2x the
complexity
clk
assign D = A && B;
always @ (posedge clk) begin
C <= D;
end
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always @ (posedge clk) begin
C <= A && B;
end
Why Code Size Matters
Designers inject approx. 1 defect per 10 lines of code
Excellent code ships with ~1 defect per KLOC
100M LOC
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Typical RTL Code
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Unstructured Verilog Code
assign …
always @(*) …
always @(*) …
always_ff @ (posedge clk …) …
assign …
always @(*) …
assign …
always_ff @ (posedge clk …) …
always @(*) …
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Unstructured Verilog Code
assign …
always @(*) …
always @(*) …
// get packet
always_ff @ (posedge clk …) …
assign …
always @(*) …
assign …
// send packet
always_ff @ (posedge clk …) …
always @(*) …
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It’s like majoring in assembly
language programming
with emphasis on the “goto”
statement
Model of Structured Code
function f ();
…
endfunction
void bar () {
task
f1 get_packet
();
();
} my_var2 <= g (…);
endtask
void foo () {
task
barsend_packet
();
();
Acts as
} my_var1 <= f (…);
“main”
endtask
main () {
always_ff
foo (); @ (posedge clk …)
}
begin
get_packet ();
send_packet ();
end
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class bar_class
() { ();
module
bar_module
…;
}
endmodule
Too much code?
class foo_class
() { ();
module
foo_module
…
}
endmodule
main () {
top_module
();
constructors
for classes
instantiate modules
……
}
endmodule
Code Size Counts – DCT Example
Verilog 95
Lines of code
1541
Files
9
Sequential
processes
6
Assign
statements
149
Combinational
processes
6
Tasks
0
Functions
0
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Code Size Counts – DCT Example
Verilog 95
Lines of code
SystemVerilog
1541
280
Files
9
1
Sequential
processes
6
1
Assign
statements
149
0
Combinational
processes
6
2
Tasks
0
4
Functions
0
8
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Code Size Counts – DCT Example
Verilog 95
Lines of code
SystemVerilog
Synthesizable C
1541
280
263
Files
9
1
1
Sequential
processes
6
1
Assign
statements
149
0
Combinational
processes
6
2
Tasks
0
4
Functions
0
8
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Real-time reactive designs (USB, PCI
Express) require a more sophisticated
form of structured design
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Structured Sequential Code - FSMs
+ { f (state, inputs) }
State machine along with a set of combinational functions
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High Level Synthesis
#include<stdio.h>
#include<stdlib.h>
int block[8][8];
void dct(){
int y,x,u,v;
int reg[8];
Q
/* Horizontal */
for(y=0;y<8;y++){
for(x=0;x<8;x++)
reg[x]=0;
CLK
for(x=0;x<8;x++){
for(u=0;u<8;u++){
v=block[y][x]*c[x][u];
v+=2048;
v>>=12;
if(s[x][u]) v=-v;
reg[u]+=v;
}
}
State
Machine
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Set of
Arithmetic
Functions
Hierarchical State Machines
+ { f (state, inputs) }
Hierarchical State machine along with a set of combinational functions
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Hardware Model of Structured Code
function f ();
…
endfunction
function g ();
…
endfunction
Sub_state
Machines
always_ff @ (posedge clk …)
case (state)
IDLE: …;
S0: begin
if (f(input_x)) doit_x();
if (doit_x_done) state<= S2;
end
endcase
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task doit_x();
doit_x_done = 0;
case (doit_x_state)
S0: …
Sn: begin
…
doit_x_done = 1;
doit_x_state = S0;
end
endcase
}
USB Example – DMA Processing
Verilog 2k
Lines of code
1600
Files
1
Sequential
processes
7
Assign
statements
30
Combinational
processes
10
Tasks
0
Functions
0
256
State Space
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About 28 pages – too
big!
Massive Concurrency
Impossibly large state
space
USB Example – DMA Processing
Verilog 2k
Lines of code
SystemVerilog
1600
1100
Files
1
1
Sequential
processes
7
2
Assign
statements
30
0
Combinational
processes
10
0
Tasks
0
2
Functions
0
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256
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State Space
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1/3 smaller
Much Less
Concurrency
Dramatically smaller
state space
Improving RTL Code
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What Students Need to Know
• How to use structure to reduce code size and
design complexity
– SystemVerilog
– Structs, enumerated types, interfaces
– Functions, tasks
• How to measure state space and understand
cost of verifying complex designs
• How to design and code hierarchical state
machines to minimize state space
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WHAT EDA NEEDS TO DO
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More Interview Questions
A
C
B
D
always @ (*) begin
C = A && B;
E = C && D;
end
E
always @ (posedge clk …) begin
W <= ……..;
Silly
end
Where’s
the latch?
always @ (posedge clk …) begin
X <= ……..;
end
Silly
always @ (posedge clk …) begin
Y <= ……..;
end
Does not
model
hardware
always @ (posedge clk …) begin
Z <= ……..;
end
(System)Verilog is not a good hardware design language –
just better than VHDL or SystemC
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No good
encapsulation
mechanism
Domain Specific Languages
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(System)Verilog is NOT Domain Specific
for Design
Verilog:
wires
reg’s (which are not registers)
SystemVerilog
bit
logic
bit_ff
A
B
Both:
whether a variable is a flop,
latch or logic gate is
determined by how it is used
reg d;
always_comb d = a | b;
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C
bit_comb
state_machine
Raising Abstraction of Design
C++/SystemC
General Purpose, High Level
Modeling Languages
Gap is too big
language, methodology, tools
Design-specific language for multiple
levels of abstraction
SystemVerilog
General Purpose Simulation Language
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It’s All Mission Critical
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It’s all about Code
Design Cost ($M)
160
140
120
Software
100
Prototype
Validation
80
Physical
60
Verification
Architecture
40
20
0
90nm
65nm
45nm
32nm
22nm
Source: IBS Design Implementation 7/09
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