Transcript Dynamic Logic - Ilam university

Dynamic Logic
Introduction
Dynamic CMOS

In static circuits at every point in time (except when
switching) the output is connected to either GND or
VDD via a low resistance path.


fan-in of n requires 2n (n N-type + n P-type) devices
Dynamic circuits rely on the temporary storage of
signal values on the capacitance of high impedance
nodes.

requires on n + 2 (n+1 N-type + 1 P-type) transistors
Dynamic Gate
Clk
Clk
Mp
off
Mp on
Out
In1
In2
In3
Clk
CL
PDN
A
C
B
Me
Clk
Two phase operation
Precharge (Clk = 0)
Evaluate (Clk = 1)
1
Out
((AB)+C)
off
Me on
Conditions on Output



Once the output of a dynamic gate is discharged, it
cannot be charged again until the next precharge
operation.
Inputs to the gate can make at most one transition
during evaluation.
Output can be in the high impedance state during
and after evaluation (PDN off), state is stored on CL
Properties of Dynamic Gates

Logic function is implemented by the PDN only




number of transistors is N + 2 (versus 2N for static complementary
CMOS)
Full swing outputs (VOL = GND and VOH = VDD)
Non-ratioed - sizing of the devices does not affect the
logic levels
Faster switching speeds



reduced load capacitance due to lower input capacitance (Cin)
reduced load capacitance due to smaller output loading (Cout)
no Isc, so all the current provided by PDN goes into discharging CL
Properties of Dynamic Gates

Overall power dissipation usually higher than static
CMOS
 no static current path ever exists between VDD and GND
(including Psc)
 no glitching
 higher transition probabilities
 extra load on Clk

PDN starts to work as soon as the input signals
exceed VTn, so VM, VIH and VIL equal to VTn


low noise margin (NML)
Needs a precharge/evaluate clock
Issues in Dynamic Design 1:
Charge Leakage
CLK
Clk
Mp
Out
CL
A
Clk
Me
Evaluate
VOut
Precharge
Leakage sources
Dominant component is subthreshold current
Solution to Charge Leakage
Keeper
Clk
Mp
A
Mkp
CL
Out
B
Clk
Me
Same approach as level restorer for pass-transistor logic
Issues in Dynamic Design 2:
Charge Sharing
Clk
Mp
Out
A
CL
B=0
Clk
CA
Me
CB
Charge stored originally on
CL is redistributed (shared)
over CL and CA leading to
reduced robustness
Charge Sharing
VDD
case 1) if V out < VTn
VDD
Clk

Mp
Mp
Out
Out
CL
A
A
==
BB
00
Clk 
CL
Ma
Ma
M
Mb
b
Mee
M
XX
a
CC
a
CC
bb
C L VDD = C L Vout  t  + Ca  VDD – V Tn  V X  
or
Ca
V out = Vout  t  – V DD = – --------  V DD – V Tn  V X  
C
L
case 2) if V out > VTn
C
 --------------------a -
Vout = –V DD 

C
+
C
 a
L
Solution to Charge
Redistribution
Clk
Mp
Mkp
Clk
Out
A
B
Clk
Me
Precharge internal nodes using a clock-driven transistor
(at the cost of increased area and power)
Issues in Dynamic Design 3:
Backgate Coupling
Clk
Mp
A=0
Out1 =1
CL1
Out2 =0
CL2
B=0
Clk
Me
Dynamic NAND
Static NAND
In
Backgate Coupling Effect
3
2
Out1
1
Clk
0
In
Out2
-1
0
2
Time, ns
4
6
Issues in Dynamic Design 4:
Clock Feedthrough
Clk
Mp
A
CL
B
Clk
Out
Me
Coupling between Out and
Clk input of the precharge
device due to the gate to
drain capacitance. So
voltage of Out can rise
above VDD. The fast rising
(and falling edges) of the
clock couple to Out.
Clock Feedthrough
Clock feedthrough
Clk
Out
2.5
In1
In2
1.5
In3
In &
Clk
0.5
In4
Clk
Out
-0.5
0
0.5
Time, ns
1
Clock feedthrough
Cascading Dynamic Gates
V
Clk
Mp
Clk
Mp
Out1
Me
Clk
Out2
In
In
Clk
Clk
Me
Out1
VTn
V
Out2
t
Only 0  1 transitions allowed at inputs!
Domino Logic
Clk
In1
In2
In3
Clk
Mp
11
10
PDN
Me
Out1
Clk
Mp Mkp
00
01
In4
In5
Clk
PDN
Me
Out2
Why Domino?
Clk
Ini
Inj
Clk
PDN
Ini
Inj
PDN
Ini
Inj
PDN
Like falling dominos!
Ini
Inj
PDN
Properties of Domino Logic


Only non-inverting logic can be implemented
Very high speed


static inverter can be skewed, only L-H transition
Input capacitance reduced – smaller logical effort
Designing with Domino Logic
VDD
VDD
VDD
Clk
Mp
Clk
Mp
Out1
Mr
Out2
In1
In2
In3
PDN
PDN
In4
Can be eliminated!
Clk
Me
Clk
Inputs = 0
during precharge
Me
Footless Domino
VDD
Clk
VDD
Mp
Clk
Mp
Out1
0
0
Clk
Mp
Out2
1
0
In1
1
VDD
Outn
1
0
In2
1
0
In3
1
0
The first gate in the chain needs a foot switch
Precharge is rippling – short-circuit current
A solution is to delay the clock for each stage
Inn
1
0
1
Differential (Dual Rail) Domino
off
Mp Mkp
Clk
Out = AB
1
on
Mkp
0
Clk
Mp
1
A
!A
0
!B
B
Clk
Me
Solves the problem of non-inverting logic
Out = AB
np-CMOS
Clk
In1
In2
In3
Clk
Mp
11
10
PDN
Me
Out1
Clk
Me
In4
In5
PUN
00
01
Clk
Mp
Out2
(to PDN)
Only 0  1 transitions allowed at inputs of PDN
Only 1  0 transitions allowed at inputs of PUN
NORA Logic
Clk
In1
In2
In3
Clk
Mp
11
10
Out1
PDN
Clk
Me
In4
In5
PUN
00
01
Clk
Me
to other
PDN’s
WARNING: Very sensitive to noise!
Mp
Out2
(to PDN)
to other
PUN’s