Transcript Chapter # 4

Elevator Controller
• We’re hired to design a
digital elevator controller
for a four-floor building
• 1st try: Design a counter
that counts up and down
• 00, 01, 10, 11, 10, 01,
00, ...
• Problem: Never stops!
11
10
• 2nd try: Add “Stop” button
that disables counter
• Problem: Have to
press button when
elevator happens by
• We need a way to have user
01
00
inputs into a complex system
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EE 1210 - Logic System Design
FSM-1
Finite State Machines
• Counters - Next state based on current state
• If counter is in state ‘101’, next state is ‘110’
• No inputs (other than reset, enable)
• Finite State Machines
• Next state is a function of the current state and the
inputs
• If the elevator is on floor 00 and the UP button is
pressed on floor 10, then move to floor 01
• If current state is 00  If UP2, Next state is 01
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EE 1210 - Logic System Design
FSM-2
A Finite State Machine
Next
State
Next floor/
direction
Current
State
State
FlipFlops
Current floor/
direction
Comb.
Logic
For
Outputs
Outputs
Motor/Door
Controls
Clock
Combinational
Logic
For Next State
Example shown for
elevator controller
Inputs
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Elevator
Buttons
EE 1210 - Logic System Design
FSM-3
Gumball Machine
•
•
We’re building a gumball machine
• 15 cents for a gumball
• Machine has a single slot, which can
take dimes or nickels
• Subcontractor provides a coin
sensor, which has two outputs:
• N is true if a nickel was input
• D is true if a dime was input
We must provide the output Open
when 15 cents entered
N
Coin
Sensor
D
Reset
Gumball
Machine
FSM
Open
Candy
Release
Mechanism
Clk
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EE 1210 - Logic System Design
FSM-4
Gumball Machine
Reset
N’D’
Diagram what is going on in a state diagram
S0
Tabulate typical input sequences:
three nickels
nickel, dime
two nickels, dime
two dimes
N’D’
dime, nickel
N’D’
N
S1
S0
S2
N
N’D’
S1
S0
[open=1]
D
N
N’D’
S2 S1
S0
D
S2
[open=1]
[open=1]
S1
[open=1]
D
S8
S7
N
N’D’
S0
S6
S5
[open=1]
N
D
N
S4
Output: open
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S2
D
N
D N’D’
Note: No
N’D’ change
provided!
D
S1
S3
Draw state diagram:
Inputs: N, D, reset
N
D
N
N’D’
S2 S1
S0
D
S2
EE 1210 - Logic System Design
Output (open) indicated
during states in which is
is asserted
FSM-5
A More Efficient Solution
Reset
0¢
N’D’
N
D
N’D’
5¢
D
N
10¢
N’D’
N+D
15+¢ D
[open=1]
N
N’D’
Reuse states
whenever possible
Symbolic State Table
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Q
D
N
Q+
Current
State
Input
Input
Next
State
0¢
0¢
0¢
0¢
5¢
5¢
5¢
5¢
10¢
10¢
10¢
10¢
15+¢
15+¢
15+¢
15+¢
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0¢
5¢
10¢
X
5¢
10¢
15+¢
X
10¢
15+¢
15+¢
X
0¢
5¢
10¢
X
EE 1210 - Logic System Design
Q
Open
Current
State
Output
0¢
0
5¢
0
10¢
0
15+¢
1
Output Table
FSM-6
Gumball Machine State Table
Encode states into binary numbers
Calculate total number of
states: 4 (0¢, 5¢, 10¢, 15¢)
Use as many bits as needed for
the states
4 states --> 2 bits
Encoding: 0¢:
5¢:
10¢:
15+¢:
00
01
10
11
Encoded State Table
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Q1 Q0
D
N
Q1+Q0+
Current
State
Input
Input
Next State
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
X
0
1
1
X
1
1
1
X
0
0
1
X
0
1
0
X
1
0
1
X
0
1
1
X
0
1
0
X
EE 1210 - Logic System Design
Q1 Q0
Open
Current
State
Output
0
0
0
0
1
0
1
0
0
1
1
1
Output Table
FSM-7
Gumball Machine Implementation
D1DN 00
Q1Q0
D
01
11
00
0
0
x
01
0
1
x
D0DN 00
10
Q1Q0
D
01
11
10
1
00
0
1
x
0
1
01
1
0
x
1
Q0
11
Q1
10
0
0
x
1
1
1
x
1
N
Q0
11
0
1
x
0
10
0
1
x
1
Q1
If we chose D
FF’s, we don’t
have to convert
Q’s to FF inputs
N
Q1 Q0
Open
Current
State
Output
0
0
0
0
1
0
1
0
0
1
1
1
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D1= D + NQ0Q1’ + Q0’Q1
D2= NQ0’ + N’Q1’Q0 + NQ1 + DQ1Q0’
Open = Q1Q0
Note that the output is a function of only the state
EE 1210 - Logic System Design
FSM-8
Inputs
• FSMs change state based on clock edges
• I.e. Rising clock edge clocks all FFs
State
FlipFlops
Comb.
Logic
For
Outputs
This part can
change only when
clock “ticks”
Clock
Combinational
Logic
For Next State
This part can change
at any time
Inputs
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Synchronous Inputs:
Change in synch with
the clock. Obey
setup and hold time.
Asynchronous
Inputs: Change at
any time. May violate
setup and hold times.
EE 1210 - Logic System Design
FSM-9
Asynchronous vs. Synchronous Inputs
• Asynchronous
• Synchronous
• Example: Elevator
• Example: Data arriving on a
pushbuttons
• Arrive at any time
• Usually asserted for many
clock cycles
• FSM logic must not make
any assumptions about
input timing
serial line from a computer
• Arrive synchronized exactly
to a clock
• One bit of data per clock
cycle
• FSM can assume that data
changes once per clock
cycle
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EE 1210 - Logic System Design
FSM-10
Parity Checker
Assert output (parity) whenever input bit stream (synchronous) has odd # of 1's
Clk
Input 0
Output 0
1
0
0
0
1
1
0
0
0
1
0
1
1
1
0
1
1
1
1
0
Reset
State
Diagram
In’
Even
[0]
In
In
Odd
[1]
In’
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Q
In
Q+
Present State
Input
Next State
Even
0
0
Even
0
Q
Parity
Present State
Output
Even
0
1
Odd
1
Even
0
0
Odd
1
0
Odd
1
Odd
1
1
Odd
1
1
Even
0
Parity = Q
Q+ = Q  In
EE 1210 - Logic System Design
FSM-11
Parity Checker
Q+ = Q  In
In
D
Q
Parity
Parity = Q
In
Pre
T
Q
Clr
Clr
Reset
Reset
D FF Implementation
Parity
T FF Implementation
• Parity Checking is a type of Synchronous Serial Input FSM
• A single input
• Input is synchronized with clock (1 bit per clock cycle)
• Goal is to look for patterns in the input bit stream
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EE 1210 - Logic System Design
FSM-12
Pattern Matcher
A string recognizer has one synchronous input (X) and one
output (Z).
The output is asserted whenever the input sequence …010…
has been observed, as long as the sequence …100… has never
been seen.
This is a synchronous serial
Sample input/output behavior:
input problem
X: 1 1 0 1 1 0 1 0 0
1. Work though sample
inputs to understand
Z: 0 0 0 0 0 0 0 1 0
problem
2. Develop FSM to
X: 0 0 1 0 1 0 1 0 0
recognize patterns
3. Implement using standard
Z: 0 0 0 1 0 1 0 1 0
techniques
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EE 1210 - Logic System Design
FSM-13
1 0
0 0
1 0
0 0
Pattern Matcher
1.
2.
Reset signal places
FSM in S0 S0
[0]
0
...0
S1
[0]
0
Reset
1
...1
S4
[0]
1
[0]
0
1
0
S2 1
...01
3.
1 S5
...10
[0]
0
1
S3 0
[1]
...010 Outputs 1
Pick a reset state.
Draw paths for strings to recognize (010
and 100)
Fill in all of the missing transitions (each
state needs a path out for 0 and 1)
S6
[0]
State S3: have recognized …010
if next input is 0 then have …0100 (state S6)
if next input is 1 then have …0101 = …01 (state S2)
State S1: recognizes strings of form …0 (no 1 seen)
loop back to S1 if input is 0
State S4: recognizes strings of form …1 (no 0 seen)
loop back to S4 if input is 1
...100
0+1
Loops in State
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State S2: if input is 1, then have …1 (state S4)
State S5: recognizes …10
if input is 1, then have …01 (state S2)
EE 1210 - Logic System Design
FSM-14
Pattern Matcher - Implementation
000 S0
[0]
0
S1 001
[0]
0
Reset
1
S4
[0]
1
100
1
0
S2 1
[0]
010
0
1.
2.
3.
[0] 101
0
1
S3
[1]
1 S5
0
011
S6 110
[0]
0+1
Assign each state a binary
number
Make the state transition table
Make the output table
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Current State Input
Q2 Q1 Q0
X
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
EE 1210 - Logic System Design
Next State
Q2 Q1 Q 0
0
0
1
1
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
1
0
0
1
1
0
0
1
0
1
1
0
1
1
0
X
X
X
X
X
X
FSM-15
Pattern Matcher - Implementation
000 S0
[0]
0
S1 001
[0]
0
Reset
Current State Output
1
S4
[0]
1
Q2
0
0
0
0
1
1
1
1
100
1
0
S2 1
[0]
010
0
1.
2.
3.
[0] 101
0
1
S3
[1]
1 S5
0
011
S6 110
[0]
0+1
Assign each state a binary
number
Make the state transition table
Make the output table
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Q1
0
0
1
1
0
0
1
1
Q0
0
1
0
1
0
1
0
1
Z
0
0
0
1
0
0
0
X
Build the FSM:
•
Use three FF’s
•
Build next state logic based on
state transition table
•
Build output logic based on
output table
EE 1210 - Logic System Design
FSM-16