Transcript Chapter # 4

Logic Chips
Actual circuit is on a
small chip of silicon
Standard chips use either
TTL (Transistor-Transitor
Logic), or CMOS
transistors
Pins are connected to
chip with internal wires
Package – Made of plastic or ceramic
Pins are numbered in a
counter-clockwise fashion
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14
2
13
3
4
5
6
7
EE 1210 - Logic System Design
HD74LS04P
Pin number one is identified
with a dot or notch
1
12
11
10
9
8
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Logic Chips – 7400 NAND
Part number – 74xx00 is a
7400 Quad Nand Gate
1
There are four 2-input
NAND gates in a 7400
13
3
12
4
5
6
7
All chips have connections
to Vcc (+5) and GND –
Usually pins 14 and 7
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14
2
74LS00
LS – Low-Power Schottky TTL
HC – CMOS
HCT – TTL-compatible CMOS
F – Fast TTL
Vcc
11
10
9
GND
EE 1210 - Logic System Design
8
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Logic Chips – Inverters and NORs
14
14
1
13
2
12
3
11
4
5
10
5
10
6
9
6
9
8
7
Vcc
74LS04
2
3
4
7
GND
74xx04 Hex Inverter
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Vcc
13
74LS02
1
12
11
8
GND
74xx02 Quad NOR Gate
EE 1210 - Logic System Design
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Logic Families
5V TTL
5V CMOS
Standard
Low-Power Schottky – LS
Fast - F
Input Voltage
5
4
3
2
1
0
Output Voltage
High
Low
5
4
3
2
1
0
High
Low
Standard - HC
HCT – TTL compatible
Input Voltage
5
4
3
2
1
0
High
Low
Output Voltage
5
4
3
2
1
0
High
Low
WARNING – Don’t
mix TTL and HC
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EE 1210 - Logic System Design
Standard Gates-4
Finding Info on Chips
• Search online
• Enter the part number, with family code
• “74LS02 datasheet”
• “74HC00 datasheet”
• Basic functionality is easy to find
• Timing info may require looking up the exact
manufacturer
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EE 1210 - Logic System Design
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Making a logic circuit
A
C
Convert to
NANDs
T1
A
C
F
A
B
T1
F
A
B
T2
B
A
T2
GND
C
GND
T2
1
2
3
4
5
6
7
1
2
3
4
5
6
7
T1
GND
GND
74LS04
74LS00
Vcc
Vcc
14
13
12
11
10
9
8
14
13
12
11
10
9
8
+5
+5
F
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EE 1210 - Logic System Design
Standard Gates-6
Prototyping Breadboards
f gh i j
+-
Connections from chip to chip
+-
Connections for Power/GND
74LS04
74LS02
74LS00
+-
+-
abcde
To +6V
+/- Are connected in columns. Used
for connections to +5V and GND.
Note: On some boards, they are split
in the middle
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a/b/c/d/e and f/g/h/i/j are connected in
rows. Used for connecting to chips.
Note: They are not connected in the
middle.
EE 1210 - Logic System Design
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