Transcript Chapter # 4

Multiplexers
A digital n-to-1 switch is called a multiplexer (or a selector)
I0
2:1
Multiplexor I1
Z = S' I0 + S I1
S=0
S=1
Two alternative forms
for a 2:1 Mux Truth Table
Z
S
0
1
S
Z
I0
I1
Functional form
Logical form
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I1
0
0
0
0
1
1
1
1
I0
0
0
1
1
0
0
1
1
S
0
1
0
1
0
1
0
1
Z
0
0
1
0
0
1
1
1
Mux-Decoder-1
Multiplexers
I0
2:1
mux
I1
Z
Z  SI 0  SI1
I0
I1
I2
I3
S
4:1
mux
S1
I0
I1
I2
I3
I4
I5
I6
I7
8:1
mux
S2
S1
Z
Z
Z  S1S0I 0  S1S0I1  S1S0I 2  S1S0I 3
S0
Z  S2 S1S0I 0  S2 S1S0I1   S2 S1S0I 2  S2 S1S0I 3 
S2 S1S0I 4  S2 S1S0I 5  S2 S1S0I 6  S2 S1S0I 7
S0
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Mux-Decoder-2
VHDL Muxes
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux4to1 IS
PORT( data : IN
sel : IN
z
: OUT
END mux4to1;
Remember the IEEE library!
STD_LOGIC_VECTOR(3 downto 0);
STD_LOGIC_VECTOR(1 downto 0);
STD_LOGIC);
Inputs: data[3..0],sel[1..0]
Output: Z
ARCHITECTURE behavior OF mux4to1 IS
BEGIN
PROCESS(data,sel) If Data or Sel change, output (Z) can change
BEGIN
Set up as a CASE statement
CASE sel IS
WHEN "00" => z <= data(0);
WHEN "01" => z <= data(1);
WHEN "10" => z <= data(2);
WHEN "11" => z <= data(3);
WHEN others => z <= 0;
WHEN OTHERS – Use this even if
END CASE;
there aren’t any others
END PROCESS;
END behavior;
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Mux-Decoder-3
Cascading Muxes
Large multiplexers can be implemented by cascaded smaller muxes
I0
I1
I2
I3
I4
I5
I6
I7
0 4:1
1 mux
2
3 S1 S0
0 4:1
1 mux
2
3 S1 S0
Control signals S1 and S0 simultaneously
choose one of I0-I3 and I4-I7
8:1
mux
0 2:1
mux
1 S
Control signal S2 chooses which of the
upper or lower MUX's output to gate to Z
Z
I0
I1
0
1 S
S0
I2
I3
0
1 S
0
1
S1 S0
S2
Alternative 8:1 Mux Implementation
S0
I4
0
I5
1 S
S0
I6
0
I7
1 S
Z
2
3 S
1
S2
S0
S1
S0
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Mux-Decoder-4
Using Muxes as logic blocks
2n-1:1 multiplexer can implement any function of n variables
n-1 control variables; remaining variable is a data input to the mux
F(C,B,A) = m0 + m2 + m6 + m7
C
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
F
1
0
1
0
0
0
1
1
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1
0
1
0
0
0
1
1
0
1
2
3
4
5
6
7
F
8:1
MUX
1
Lookup Table
S2 S1 S0
C
B
A
0
1
0
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Mux-Decoder-5
Optimized LUTs
F(C,B,A) = m3 + m4+ m6 + m7
CB=00; F=0
CB=01; F=A
CB=10; F=A’
CB=11; F=1
C
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
F
0
0
0
1
1
0
1
1
0
A
A
0
A
A
1
0
1
2
3
F
4:1
MUX
S1
C
S0
B
1
We can fit a function of n variables into a 2n-1:1 mux by using this trick
(note: may require one inverter)
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Mux-Decoder-6
Using a multiplexor as a switch
Consider a computer system with CPU, memory, I/O devices, etc.
Each one needs to be able to communicate with the others…
Memory
CPU
Disk
Keyboard
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Pros:
• Conceptually simple
32
32
32
32
4:1 x
32bit
Mux
32
00
Control
Cons:
• Lots of wires…
• Each device needs
separate output and
input ports
• 32-bit mux is a large
device
Example: Read a value
from memory into CPU
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Mux-Decoder-7
Using a Bus
32
A few (2-3) control
lines to each device
Memory
CPU
32
32
Control
Disk
Keyboard
Critical issue: We’re
connecting multiple outputs
together. Bad Idea!
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32
32
Bus – Bidirectional, Driven
by one device at a time
Pros:
• Much fewer wires
• Simpler wiring
• Expandable
• One data port per
device
Cons:
• More complex
electrically
• Must manage bus
Example: Read a value
from memory into CPU
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Mux-Decoder-8
Smoke Happens…
+5V
+5V
OK to connect one output to multiple inputs
1
0
Not OK to connect outputs together!
Direct connection from power to
ground – smoke!
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Mux-Decoder-9
Tri-State Inverter
5V
In
Out
En=1
In
Out
Enable
In
Out
High-Impedance
(Hi-Z) state
En=0
0V
Modify an inverter…
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In
Out
En
Out
En
0
Z
Tri-state Inverter
1
In’
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Mux-Decoder-10
Using tri-state gates
Goal: Connect three selectable
inputs to a common output
in0
sel0
in1
Whenever a select signal is asserted,
that input is connected to the output
sel1
in2
sel2
out
Must make sure that there is always exactly one driver turned on!
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Mux-Decoder-11
Demultiplexers
Demultiplexer: One data input, n control inputs, 2n outputs
Control inputs (called selects) - Binary index of output to which
the input is connected
Data input usually called “enable” (‘G’ or ‘E’)
1:2 Demultiplexer:
G
O0
O1
G
S
O0
O1
O0 = G • S; O1 = G • S
S
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Mux-Decoder-12
Larger Demultiplexers/Decoders
O0
O1
O2
G
O3
S1 S0
1:8 Demultiplexer
3:8 Decoder
O 0 = G • S 2 • S1 • S 0
1:4 Demultiplexer
O 1 = G • S 2 • S1 • S 0
2:4 Decoder
O 2 = G • S 2 • S1 • S 0
O 0 = G • S 1 • S0
O3 = G • S2 • S1 • S0
O 1 = G • S 1 • S0
O 4 = G • S 2 • S1 • S 0
O 2 = G • S 1 • S0
O 5 = G • S 2 • S1 • S 0
O3 = G • S1 • S0
O6 = G • S2 • S1 • S0
O 7 = G • S2 • S1 • S0
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O0
O1
O2
O3
G
O4
O5
O6
O7
S2 S1 S0
If we view the ‘G’ signal as an
enable, then a demultiplexer
simply decodes the binary
select signal into a unary output
signal  Decoder
Decoder:
• Enable=0 all outputs are 0
• Enable=1 output is unary
representation of binary select
input
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Mux-Decoder-13
Decoders In VHDL
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Decoder2to4 IS
PORT( s
: IN
STD_LOGIC_VECTOR(1 downto 0);
en : IN
STD_LOGIC;
y
: OUT
STD_LOGIC_VECTOR(3 downto 0));
END Decoder2to4;
ARCHITECTURE logicfunc OF Decoder2to4 IS
BEGIN
PROCESS(s,en)
Sensitive to changes in s or en
BEGIN
IF (en=‘1’) THEN
Only consider when en = ‘1’
CASE (s) IS
WHEN “00” => y <= “0001”;
WHEN “01” => y <= “0010”;
Go through cases for all
WHEN “10” => y <= “0100”;
possible inputs
WHEN “11” => y <= “1000”;
WHEN OTHERS => y <= “0000”;
END CASE;
ELSE y <= “0000”;
If en = ‘0’, then output “0000”
END IF;
END PROCESS;
END logicfunc;
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Mux-Decoder-14
Encoders
Encoders are the opposite of decoders
Unary input w[7..0] –
exactly one of the eight
inputs is ‘1’
w0
y0
w1
y1
w2
y2
w3
w4
w5
w6
8-3
w7
Encoder
Binary output y[2..0] –
Corresponds to the
index of the input that is
‘1’
For an 8-3 encoder, there should be 256 rows in the truth table
Only rows with exactly one ‘1’ are valid  Eight valid rows
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Mux-Decoder-15
Priority Encoders
What if more than one input to and encoder is ‘1’?
 Invalid input  Output is undefined
Higher Priority
Priority Encoder:
If more than one input is ‘1’, more significant bit has priority
Add a ‘z’ output  true when no inputs are ‘1’
0
1
0
0
1
0
1
0
w0
y0
w1
y1
w2
y2
w3
w4
z
w5
8-3
w6
w7 Priority
Encoder
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0
1
1
0
6
w7
0
0
0
0
0
0
0
0
1
w6
0
0
0
0
0
0
0
1
x
w5
0
0
0
0
0
0
1
x
x
w4
0
0
0
0
0
1
x
x
x
w3
0
0
0
0
1
x
x
x
x
w2
0
0
0
1
x
x
x
x
x
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w1
0
0
1
x
x
x
x
x
x
w0
0
1
x
x
x
x
x
x
x
y2
x
0
0
0
0
1
1
1
1
y1
x
0
0
1
1
0
0
1
1
y0
x
0
1
0
1
0
1
0
1
z
1
0
0
0
0
0
0
0
0
Mux-Decoder-16
VHDL Priority Encoder
LIBRARY ieee;
USE ieee.std_logic_1164.all;
Remember the IEEE library!
ENTITY Priority8 IS
PORT( w
: IN
STD_LOGIC_VECTOR(7 downto 0);
y
: OUT
STD_LOGIC_VECTOR(2 downto 0);
z
: OUT
STD_LOGIC);
Input: w[7..0]
END Priority8;
Outputs: y[2..0], Z
ARCHITECTURE behavior OF Priority8 IS
BEGIN
PROCESS(w)
Case statement would require 256 rows…
BEGIN
IF
(w(7)=‘1’) THEN y <= “111”; z <= ‘0’; Use cascaded IFs
ELSIF (w(6)=‘1’) THEN y <= “110”; z <= ‘0’;
ELSIF (w(5)=‘1’) THEN y <= “101”; z <= ‘0’;
ELSIF (w(4)=‘1’) THEN y <= “100”; z <= ‘0’;
ELSIF (w(3)=‘1’) THEN y <= “011”; z <= ‘0’;
ELSIF (w(2)=‘1’) THEN y <= “010”; z <= ‘0’;
ELSIF (w(1)=‘1’) THEN y <= “001”; z <= ‘0’;
ELSIF (w(0)=‘1’) THEN y <= “000”; z <= ‘0’;
ELSE
y <= “000”; z <= ‘1’;
END IF;
END PROCESS;
END behavior;
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Mux-Decoder-17