Transcript ee1210 - Daniels - Chapter3 - Seattle Pacific University

Arithmetic and CAD Tools
• CAD tools work great with arithmetic functions
• Adding,subtracting,multiplying, etc.
• A few things to learn first
• How to work with multi-bit numbers in CAD tools
and VHDL
• How to create custom components in CAD tools
• I.e. a 7-bit adder/subtractor
• How to include VHDL components in a larger
schematic
Seattle Pacific University
EE 1210 - Logic System Design
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Multi-bit Numbers - Busses
• In Quartus II Schematics
• Busses are collections of wires
• mybus[7..0] is an eight bit bus
• Composed of mybus[7] (MSB) through mybus[0]
(LSB)
• Busses make it easier to draw circuit diagrams
• In VHDL
• Busses are defined as a type of STD_LOGIC
• X: STD_LOGIC_VECTOR (7 DOWNTO 0)
• Composed of X(7) through X(0)
Seattle Pacific University
EE 1210 - Logic System Design
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Connecting by name in Schematics
• Nodes (wires) can be
connected by name
• Reduces complexity of
drawing
• Input names
• Can be used on any wires
• All wires of the same
name are connected
• Intermediate node names
• Just name it – no need to
define it
• Busses
• Can connect a single wire
from a bus by name
Seattle Pacific University
EE 1210 - Logic System Design
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Busses in Schematics
• Many components have
bus inputs
• Adders, for example
• Busses use thick lines
• Drawing from a bus input
automatically makes a bus
• May select thick line from
the line style menu
• Connecting busses
• Just name them the same
thing
• Making busses out of wires
• Type all of the components
(MSB to LSB) separated by
commas
Seattle Pacific University
EE 1210 - Logic System Design
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Creating and Using Custom Schematic Symbols
1. Make your
component.
Inputs/Outputs are
interface to higher
level
2. File | Create/Update
| Create Symbol File
For Current File
3. Make a new
schematic for your
main file and use
your new symbol!
Seattle Pacific University
EE 1210 - Logic System Design
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Making and Using Custom VHDL Symbols
1. Make your
component.
Inputs/Outputs are
interface to higher
level
2. File |
Create/Update |
Create Symbol File
For Current File
3. Make a new
schematic for your
main file and use
your new symbol!
Seattle Pacific University
EE 1210 - Logic System Design
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MegaFunctions
• Quartus II has many
configurable megafunctions
• Adders, subtractors, muxes,
etc.
• Use the MegaWizard
• Button on the insert
symbol menu
• Answer all of the questions
• see next slide…
• Save the new part
• Insert it into your schematic
Seattle Pacific University
EE 1210 - Logic System Design
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Using the MegaWizard
1. Choose “Create a new…” to
make a new device
2a. Pick a megafunction to use:
Arithmetic includes adders,
subtractors, counters, multipliers,
etc.
Gates include multiple-bit
variations of standard logic.
2b. Choose VHDL and give your
part a name.
Seattle Pacific University
EE 1210 - Logic System Design
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Using the MegaWizard
3. Pick options:
Data bus width
Modes
Etc.
Seattle Pacific University
EE 1210 - Logic System Design
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Using the MegaWizard
4. Decide if any
inputs are constants
(i.e. always adding
4)
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EE 1210 - Logic System Design
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Using the MegaWizard
5. Pick optional
outputs:
Adder has optional
carryin, carryout,
and overflow out.
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EE 1210 - Logic System Design
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Using the MegaWizard
6. Pipelining –
advanced option to
speed up the
function. Don’t use
for now.
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EE 1210 - Logic System Design
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Using the MegaWizard
7. Just click
Finish…
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EE 1210 - Logic System Design
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Using the MegaWizard
9. Now your new
symbol is available for
use in schematics!
8. Yes – add to
your project so you
can use it!
Seattle Pacific University
EE 1210 - Logic System Design
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Using Busses in VHDL
Must use the IEEE library to use STD_LOGIC
LIBRARY ieee;
USE ieee.std_logic_1164.all;
Bus definition
ENTITY hextosevenseg IS
PORT( N
: IN
STD_LOGIC_VECTOR(3 downto 0);
a,b,c,d,e,f,g,dec
: OUT
STD_LOGIC);
END hextosevenseg;
ARCHITECTURE logicfunc OF hextosevenseg IS
BEGIN
a <= NOT(
(N(2) AND N(1) AND NOT N(3)) OR
(N(1) AND NOT N(2) AND N(0))
);
b <= …
Using bus signals individually
END logicfunc;
Seattle Pacific University
EE 1210 - Logic System Design
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Math in VHDL
Must use the SIGNED library for math
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
ENTITY addemup IS
PORT( A,B : IN
Sum : OUT
END addemup;
STD_LOGIC_VECTOR(15 downto 0);
STD_LOGIC_VECTOR(15 downto 0));
ARCHITECTURE logicfunc OF addemup IS
BEGIN
Sum <= A + B;
END logicfunc;
We’re adding two 16-bit numbers
and producing a 16-bit sum
It’s this easy!
Seattle Pacific University
EE 1210 - Logic System Design
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Decisions in VHDL using IF/THEN/ELSE
LIBRARY ieee;
Expand adder to adder/subtractor:
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all; Sub=‘1’  subtract, Sub=‘0’  Add
ENTITY addemup
PORT( A,B
Sub
Out
END addemup;
IS
: IN
STD_LOGIC_VECTOR(15 downto 0);
: IN STD_LOGIC;
: OUT
STD_LOGIC_VECTOR(15 downto 0));
ARCHITECTURE logicfunc OF addemup IS
BEGIN
PROCESS: Identify which inputs may
PROCESS(Sub,A,B)
cause output to change
BEGIN
IF (Sub = ‘0’)THEN
Scalar constants
Out <= A + B;
IF / ELSIF / ELSE / END IF;
in single quotes ELSIF (Sub = ‘1’)THEN
Decision-making statements
Out <= A – B;
Vector constants ELSE
Out <= “0000000000000000”;
in double quotes
END IF;
END PROCESS;
Don’t forget to END IF and PROCESS
END logicfunc;
Seattle Pacific University
EE 1210 - Logic System Design
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Truth Tables in VHDL
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY simplefunction IS
PORT( A
: IN
STD_LOGIC_VECTOR(1 downto 0);
Z,Q : OUT
STD_LOGIC);
END simplefunction;
ARCHITECTURE logicfunc OF simplefunction IS
BEGIN
PROCESS(A)
Process block specifies input(s) to process
BEGIN
CASE A IS
Vector constants
WHEN “00” => z<=‘0’;q<=‘0’;
in double quotes
WHEN “01” => z<=‘1’;q<=‘1’;
WHEN “10” => z<=‘1’;q<=‘1’;
Scalar constants
A case for each row
WHEN “11” => z<=‘0’;q<=‘1’;
in single quotes
in truth table
WHEN OTHERS =>z<=‘0’;q<=‘0’;
END CASE;
END PROCESS;
END logicfunc;
“Others” catches any unlisted cases.
Use it even if you covered them all.
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EE 1210 - Logic System Design
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