Transcript Moore Machines - Seattle Pacific University

Moore Machines
Current State
Next State
State
FlipFlops
Clock
Combinational
Logic
For Next State
Comb.
Logic
For
Outputs
Outputs
A Moore FSM –
Outputs are a
function of ONLY
the current state
Reset
0¢
N’D’
N
Inputs
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Open
Current
State
Output
0¢
0
5¢
0
10¢
0
15+¢
1
EE 1210 - Logic System Design
N’D’
5¢
D
Q
D
N
10¢
N’D’
N+D
15+¢ D
[open=1]
N
N’D’
MooreMealy-1
Mealy Machines
Current State
Next State
State
FlipFlops
Comb.
Logic
For
Outputs
Outputs
Clock
Combinational
Logic
For Next State
Inputs
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A Mealy FSM –
Outputs are a
function of the
current state and
inputs
WARNING – Outputs are no longer
synchronized with clock
EE 1210 - Logic System Design
MooreMealy-2
Mealy FSM Diagrams
In a Mealy FSM, the outputs depend
on the current state and the inputs
We can’t just label the states with
the outputs anymore.
Reset
0¢
D/0
N’D’/0
N/0 N’D’/0
Outputs are associated with ARCS
(transitions between states)
Arc Labeling:
Input(s)/Output(s)
5¢
D/1
N/0
N’D’/0
10¢
N+D/1
15+¢ D/0
N/0
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EE 1210 - Logic System Design
N’D’/0
MooreMealy-3
Mealy FSM Diagrams - Efficiency
Examine the 15+¢ state:
But, in Mealy FSMs, we don’t
use states for outputs  The
15+¢ state is not needed!
We spend almost no time in it –
it’s purpose was to output the
signal OPEN
Reset
Reset
0¢
N’D’
N
D
0¢
N’D’
N’D’/0
N/0 N’D’/0
N’D’/0
N/0 N’D’/0
5¢
5¢
5¢
D
Reset
D/1
N/0
10¢
N’D’/0
15+¢ D
[open=1]
N
N/0
10¢
N’D’/0
N’D’
Moore
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15+¢ D/0
N/0
10¢
N+D/1
N+D/1
N+D
D/0
D/1
N
N’D’
0¢
D/0
Efficient
Mealy
N’D’/0
Mealy
EE 1210 - Logic System Design
MooreMealy-4
Mealy Gumball Machine – Table Form
Present Inputs
State
Reset
0¢
00
D/0
N’D’/0
N/0 N’D’/0
5¢
01
D/1
N/0
N’D’/0
10¢
10
N+D/1
Efficient
Mealy
Assign numbers to
states
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Next State
Q1 Q0 D N Q1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
X
0
1
0
X
1
0
0
X
X
X
X
X
+
Q0
0
1
0
X
1
0
0
X
0
0
0
X
X
X
X
X
+
Output
Notice that Output is
now a function of
state and inputs
Open
0
0
0
X
0
0
1
X
0
1
1
X
X
X
X
X
Only using three
states – State 11 is
all don’t cares
EE 1210 - Logic System Design
MooreMealy-5
Mealy Gumball
Machine
Implementation
D
D
D1DN 00
Q1Q0
01
11
10
D0DN 00
Q1Q0
01
11
10
00
0
0
x
1
00
0
1
x
0
01
0
1
x
0
01
1
0
x
0
Q0
11
Q1
10
x
x
x
x
1
0
x
0
N
Open
DN 00
Q1Q0
00
0
01
0
10
x
x
x
10
0
1
x
1
0
x
0
D1= DQ1’Q0’ + NQ0 + D’N’Q1
D2= NQ0’ + D’N’Q0 + DQ1
1
Q0
11
x
x
x
x
10
0
1
x
1
Q1
x
N
11
x
11
Q1
D
01
0
Q0
If we chose D
FF’s, we don’t
have to convert
Q’s to FF inputs
Open = DQ0 + NQ1 + DQ1
Note that the output is a function of
the state and the inputs
N
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EE 1210 - Logic System Design
MooreMealy-6
Pattern Matcher – Moore and Mealy
Machine that outputs 1 when last three inputs
were “010”, unless “100” has ever been seen
Reset
S0
[0]
1
...0
0
...0
...1
S1
[0]
S4
[0]
0
1
[0]
...01
0
1
S5
[0]
0
...010
Moore
S6
[0]
1/0
0/0
1
1/0
0/0
S2 1/0
...10
...01
1/0 S5
...10
0/1
0/0
...100
S6
...100
(0+1)/0
0+1
The purpose of state S3 is to
output ‘1’ – can we get rid of it?
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...1
S4
0
1
S3
[1]
1/0
0/0
S1
0
S2 1
Reset/0
S0
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Mealy
MooreMealy-7
Pattern Matcher - A Better Way?
If last three bits were 010, output 1 unless 100 has ever been seen.
Q2Q1Q0 are the last three bits shifted in (in that order)
Q2
Q1
Q0
Shift Register
En
clk
If last three bits were 100,
enable is turned off and all
shifting stops
Shift in
X
Q2 Q1 Q0
Q2 Q1 Q0
Q2
Q1
Q0
Z
Outputs Z=1 if sees 010
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EE 1210 - Logic System Design
MooreMealy-8
VHDL Pattern Matcher - Moore
BEGIN
PROCESS(reset,clk)
S0
BEGIN
[0]
1
if (reset=‘1’) then state <= S0;
0
...0
...1
elsif (rising_edge(clk)) then
S4
S1
case state is
[0]
[0]
when S0 =>
1
0
if (x=‘1’) then state <=S4;
1
0
else state <=S1;
...10
end if;
S2 1
S5
State
machine

1
when
S1 =>
[0]
...01 [0]
One big case
if (x=‘1’) then state <=S2;
0 1
0
else state <=S1;
statement!
end if;
...100
S3 0
S6
when S2 =>
[1]
[0]
0+1
if (x=‘1’) then state <=S4;
...010
else state <=S3;
end if;
when S3 =>
LIBRARY ieee;
if (x=‘1’) then state <=S2;
USE ieee.std_logic_1164.all;
else state <=S6;
end if;
ENTITY patternmatch IS
when S4 =>
PORT(
if (x=‘1’) then state <=S4;
clk: IN STD_LOGIC;
else state <=S5;
end if;
reset: IN STD_LOGIC;
when
S5 =>
x: IN STD_LOGIC;
if
(x=‘1’)
then state <=S2;
z: OUT STD_LOGIC);
else
state
<=S6;
END patternmatch;
end if;
ARCHITECTURE behavior OF patternmatch IS
when S6 =>
Type state_type is (S0,S1,S2,S3,S4,S5,S6);
state <=S6;
end case;
SIGNAL state: state_type;
end if;
If (state = S3) then z <= ‘1’;
Declare possible states
else z<=‘0’;
end if;
Output Z depends on state (Moore) end process;
END behavior;
Reset
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MooreMealy-9
VHDL Pattern Matcher - Mealy
BEGIN
PROCESS(reset,clk)
BEGIN
1/0
0/0
if (reset=‘1’) then state <= S0;
elsif (rising_edge(clk)) then
S4
S1
case state is
when S0 =>
1/0
0/0
if (x=‘1’) then state <=S4;z<=‘0’;
1/0
0/0
else state <=S1; z<=‘0’;
1/0
end if;
State
machine

S2
S5
1/0
when S1 =>
One big case
if (x=‘1’) then state <=S2;z<=‘0’;
0/1
else state <=S1; z<=‘0’;
0/0
statement!
end if;
S6
when S2 =>
if (x=‘1’) then state <=S4;z<=‘0’;
(0+1)/0
else state <=S5; z<=‘1’;
end if;
LIBRARY ieee;
when
S4 =>
USE ieee.std_logic_1164.all;
if (x=‘1’) then state <=S4;z<=‘0’;
else state <=S5; z<=‘0’;
ENTITY patternmatch IS
end if;
when S5 =>
PORT(
if (x=‘1’) then state <=S2;z<=‘0’;
clk: IN STD_LOGIC;
else state <=S6; z<=‘0’;
reset: IN STD_LOGIC;
end if;
x: IN STD_LOGIC;
when S6 =>
z: OUT STD_LOGIC);
state <=S6; z<=‘0’;
No More S3!
END patternmatch;
end case;
ARCHITECTURE behavior OF patternmatch IS end if;
end process;
Type state_type is (S0,S1,S2,S4,S5,S6);
END behavior;
SIGNAL state: state_type;
S0
Reset/0
Declare possible states
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Output Z depends on state and
input.
EE 1210 - Logic System Design
MooreMealy-10
Review of FSM Design Process
• Write down sample inputs and outputs to
understand specification
• Write down sequences of states and transitions for
the sequences to be recognized
• Add missing transitions; reuse states as much as
possible
• Verify I/O behavior of your state diagram to ensure it
functions like the specification
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EE 1210 - Logic System Design
MooreMealy-11
Complex Counter
A synchronous 3 bit counter has a mode control M. When M = 0, the
counter counts up in the binary sequence. When M = 1, the counter
advances through the Gray code sequence.
Binary: 000, 001, 010, 011, 100, 101, 110, 111
Gray: 000, 001, 011, 010, 110, 111, 101, 100
Valid I/O behavior:
Mode Input M
0
0
1
1
1
0
0
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Current State
000
001
010
110
111
101
110
Next State (Z2 Z1 Z0)
001
010
110
111
101
110
111
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MooreMealy-12
Complex Counter
Reset
Counter
 Output is the state
 Moore Machine
0
0
000
0
001
1
111
1
1
0
010
1
1
1
011
0
1
0
110
101
1
0
100
0
Input M=0 --> Binary; M=1 --> Gray Code
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EE 1210 - Logic System Design
MooreMealy-13
Digital Combination Lock
A 3-bit serial combination lock is used to allow entry into a locked room.
The lock has RESET button, an ENTER button, and a two-position switch
to represent the key being entered. When the signal UNLOCK is asserted,
an electromechanical relay is released, allowing the door to open. The
unlock process begins when the operator presses RESET. He or she then
sets the input switch, followed by pressing the ENTER button. This is
repeated for the second and third key digits. An ERROR light should be
illuminated if, after entering the three binary digits, the operator has not
matched the key. The process can be started again by hitting reset again.
Reset
Enter
1
0
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Unlock
Error
MooreMealy-14
An assumption
• Somehow, we have to know what the secret
combination is
• We could embed this in a FSM
• We could have it in a register, which is set by some
(undefined) input combination
• We’ll go with option 2
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EE 1210 - Logic System Design
MooreMealy-15
Digital Combination Lock
Reset
Mealy machine:
PROM
A
B
C
Enter’
Enter  I=CA
CA
CB
CC
Enter 
I !=CA
start
Enter’
Enter’
Enter  I=CB
Good1
Enter 
I !=CB
Enter
Enter’
Enter’
Enter 
Enter  I=CC Good2
I !=CC
Bad1
Bad2
Enter
Good3
Bad3
Reset’/Error
Reset’/Unlock
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EE 1210 - Logic System Design
MooreMealy-16
Party Machine
• Design a system that changes the radio station
automatically if it appears that people are bored
• Assume: People that don’t move around are bored
• Define boredom: If nobody has moved in the past
five seconds, everybody is bored
• Parameters
• Inputs:
• Motion detector that outputs the signal M
whenever motion occurs
• 1-second clock
• Output: Two bit signal for the current radio station
(four choices…)
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EE 1210 - Logic System Design
MooreMealy-17
Party Machine Implementation
Output: Number of radio station
M
M
M
0s
[00]
M’
M
1s
[00]
M’
M
M
2s
[00]
M
3s
[00]
4s
[00]
0s
[01]
M’
M
1s
[01]
M
2s
[01]
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M
M
3s
[01]
4s
[01]
0s
[10]
M’
M
1s
[10]
M
2s
[10]
M
M
3s
[10]
4s
[10]
1s
[11]
2s
[11]
M’
M’
M’
0s
[11]
M’
M’
M’
M’
M’
M
M’
M’
M’
M
M
M’
M’
M
Input: M (motion detected)
One-second clock
3s
[11]
M’
M’
EE 1210 - Logic System Design
M
4s
[11]
M’
MooreMealy-18
Party Machine - Alternative
Change machine1 to output B (Boring) Signal
M
M
0s
[B’]
M’
Create a second machine to change station:
Input: B; Output: Station
B’
1s
[B’]
0s
[00]
B
M’
M
2s
[B’]
1s
[01]
M’
M
3s
[B’]
B
M+M’
4s
[B’]
M’
B’
2s
[10]
M’
M
B’
B
B
B’
3s
[11]
5s
[B]
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EE 1210 - Logic System Design
MooreMealy-19
VCR controller
Implement a VCR controller as a Moore FSM.
The user controls the motion as follows:
Pressing the Play button causes the tape to play.
Pressing the FF button causes the tape to advance:
Without playing, if stopped.
Scanning, if in play mode.
Pressing the Stop button causes the tape to stop.
Pressing the Rew button causes the tape to rewind:
Without playing, if stopped.
Scanning, if in play mode.
Note: I haven’t specified all transitions possible...
Outputs: Forward, Reverse, Fast, HeadReading
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EE 1210 - Logic System Design
MooreMealy-20
Airlock controller
Implement an airlock controller as a Moore FSM.
The airlock has two doors – insideDoor and outsideDoor. These
are controlled by the signals insideDoorOpen and
outsideDoorOpen.
There are two buttons – insideRequest and outsideRequest.
The airlock pressure is controlled by a single signal – pressurize.
The pressurize/depressurize process takes 10 seconds.
A ten second timer is available. It has input StartTimer and output
TimeUp.
The reset state is:
Both doors closed. Airlock pressurized.
When a request button is pressed, the following must happen:
1. The chamber is either pressurized or depressurized depending
on which button was pressed.
2. The appropriate door is opened for ten seconds and then
closed.
3. The chamber’s pressure is inverted.
4. The opposite door is opened for ten seconds and then closed.
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EE 1210 - Logic System Design
MooreMealy-21
Combo Lock #2
Design another combo lock controller as a Mealy FSM...
The combination is A-A-B-A-B-A. If this is entered, output “open”.
From any state, three B’s in a row will reset the lock to it’s
beginning state.
Whenever an out-of-sequence A occurs, an output “bell” is
asserted to raise an alarm.
Once the lock is open, pressing either A or B will reset it to the
beginning state.
Note: This is a poor security design
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EE 1210 - Logic System Design
MooreMealy-22
Washing Machine
Design a washing machine controller as a Moore FSM...
Operation: When start is pressed, goes through wash, spin, rinse, spin cycles.
If “double rinse” is selected, an extra rinse and spin cycle is added.
Details: Must fill the tub with water before washing or rinsing – output the
signal “filltub” to do this. A timer is provided that gives the appropriate amount
of time for a wash, rinse, or spin cycle.
Outputs:
Filltub – turns on water to tub.
Agitate – turns on agitator for wash and rinse
Spin – turns on spinner
StartTimer – starts the wash/rinse/spin timer – the timer’s start input is risingedge triggered
Inputs:
Start – starts a wash
Tubfull – true when tub is full of water
Double – true if user wants a double rinse
TimeUp – true when time for wash/rinse/spin is done
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EE 1210 - Logic System Design
MooreMealy-23
Tennis Scorer
Design a Moore finite state machine that keeps track of score in a
tennis game. Tennis is scored as follows:
• There are two players, A and B.
• Scoring starts at zero, which is known in tennis lingo as love.
• As a player wins games, his/her score advances as follows:
Love  15  30  40  Game
• The first one to achieve “Game” wins.
• The score 40-40 is known as deuce. If the score is deuce,
then the first player to win two points in a row wins the game.
Your finite state machine will have synchronous inputs A, which is true
whenever A wins a point, and B, which is true whenever B wins a
point, and a reset input.
The outputs should be “A wins” and “B wins”, asserted at the
appropriate times. Each state should be labeled with the current
score of player A and player B (i.e. 15-Love or 40-15).
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EE 1210 - Logic System Design
MooreMealy-24