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EMC Models
Summary
1. Models, what for ?
2. EMC of IC Model
3. Core Model
4. Package models
5. Emission measurements/simulations
6. Immunity measurements/simulations
7. Chip-to-chip Coupling
8. Future of EMC models
9. Conclusion
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July 15
Models – What for ?
IC designers want to predict EMC before fabrication
Noise margin
Switching Noise on Vdd
• IC designers want to predict power integrity and EMI during design cycle
to avoid redesign
• EMC models and prediction tools have to be integrated to their design
flows
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July 15
Models – What for ?
Equipment designers want to predict EMC before fabrication
© Siemens Automotive Toulouse
• Most of the time, EMC measurements are performed once the equipment
is built.
• No improvements can be done at conception phase.
• Predict EMC performances  IC, board, equipment optimizations
• However, need of non-confidential IC models (black box models)
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July 15
EMC of IC models
EMC Models depends on the targeted complexity, the level of
confidentiality of information.
Level
Equipment
Board
V, Z
100 V(f), 100 Z(f)
101 dipoles
Dipoles
Component
ICEM
101 R,L,C,I
LEECS
Physical
102 R,L,C,I
Expo
low
medium
104 R,L,C,I
PowerSI
high
spice
x-high
106 R,L,C,I
Complexity
Confidentiality
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July 15
EMC of IC model
The model of an IC can be derived from its physical architecture.
It includes the core and package model.
Model of the die :
• internal activity (core)
• on-chip decoupling
• supply network
• I/O structure
Core
IC
Core
Model of the package using R,L,C
Package
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July 15
EMC of IC models
General flow to build an EMC model and predict EMC performances
Test bench Model
Test board Model
Package Model
Core – I/O
Model
EMC Model for
the circuit
Simulated Emission
spectrum
Electrical
Simulation
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July 15
EMC of IC models
How establishing an EMC of IC model ?
info
From layout
From floorplan
estimation
block
Without IC confidential
information
Internal
Activity

I(t) simulation

Estimated current source
model for each block

External i(t) measurement 
internal current extraction
On-chip
decoupling

Layout extraction

Estimated on-chip
capacitance for each block

S parameter measurements
Supply
Network

RC Layout
extraction

RC Layout extraction


S parameter measurements
Power supply placement from
datasheet

I(V) characteristic from IBIS file
I/O
Full
model of I/O
Measurement
 3D EM simulation
 IBIS package data

Package
Objectives

Accurate prediction,
check EMC
performances

Feasibility study, 1st noise
evaluation, optimization of onchip and supply pairs placement
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July 15

Provide model to predict
EMC compliance of an
entire system
Package Model
3D Electromagnetic solver
S
Electromagnetic
solver
 Method of moment
 S11
S
 21
 S31
S12
S 22
S32
S13 
S 23 
... 
S parameter black box
 FEM
Geometrical meshed model
 FDTD
 PEEC…
 Simulation of EM behavior of packages
 Extraction of package model
 Electrical models compatible with electrical simulator
(SPICE-like)
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July 15
 R11  jL11
 R  jL
21
 21
 R31  jL31
R12  jL12
R22  jL22
R32  jL32
RLC matrix
R13  jL13 
R23  jL23 

...
Package Model
S parameters extraction
Coplanar probe
Vector Network Analyzer
Package
 Extraction of package model from measurement
 Calibration plane issues from hundreds of MHz
 Require good knowledge in RF measurement
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July 15
Core model
Supply network model

Complex network of interconnections, vias and on-chip capacitances
 Coupling path for noise through the IC
 Require extraction of impedance between Vdd and Vss.
 Possible modeling by an equivalent passive model
Equivalent passive model
Substrate, interconnections
metallization
Capacitive
behavior
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July 15
Core model
Model core activity : extract noise source
32 bit
processor
500 MHz
16 bit
processor
16 MHz
Extraction of internal current waveform
I
I
3A
100 mA
time
time
62.5 ns
2 ns
1st order assumption : model core activity by triangular waveform current source
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July 15
Core model
Model core activity: noise source
Physical Transistor
level (Spice)
Interpolated
Transistor level
Gate level Activity
(Verilog)
Activity estimation
from data sheet
Huge simulation
Limited to analog blocks
Difficult adaptation to
usual tools
Limited to 1 M devices
Simple, not limited
Fast & accurate
Very simple, not limited
Immediate, not accurate
Activity1200
1000
800
600
400
200
00
Extraction
20
40
60
80
100
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120
July 15
140
time (ns)
Equivalent
Current
generator
Core model
Model The IC using a complete power supply distribution network
Chip model
Package model
Package model
Floorplanning,
physical layout
Vdd2
Chip
model
Vss2
Vdd1
Elementary cell
Vss1
 Full chip switching noise analysis, mapping of voltage drop, evaluation of
power integrity, crosstalk, EMI, effect of on-chip decoupling.
 Very accurate but large netlists.
 Too much complex to add PCB model.
 Adapted for IC designer issues.
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July 15
Core model
Model core activity: Tool example
Layout
Silicium voltage drop map
PowerSI - Real-time voltage noise simulation (right), including on-chip
decoupling capacitors, shows a more stable on-chip power supply © Sigrity
http://www.sigrity.com
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July 15
Core model
Model The IC using double LC system
Example of measurement of IC conducted emission
Emission
Level (dBµV)
1st resonance
Envelop of spectrum
2nd resonance
Frequency
(MHz)
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July 15
Core model
Model The IC using double LC system
IC model
Package model
ICEM model
(IEC 62014-3)
External
VDD
External
VSS
Rvdd
Lvdd
LPackVdd
Cd
LPackVss
Cb
Rvss
Primary
resonance
Ib
Lvss
Secondary
resonance
Emission
level
Low L,C values =>
High resonant frequency
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July 15
Frequency
IO Model
IBIS: Input Buffer I/O specification
[Component] Fx45H725
IBIS
[Manufacturer] Finex
[Package]
| variable typ min max
|
R_pkg 800m 500m 950m
L_pkg 6nH 5.5nH 7.5nH
C_pkg 8pF 4pF 10.5pF
[Pin] signal model R_pin L_pin C_pin
1 /1OE in1 921m 7.25nH 10.1pF
2 1Y1 out 1 916m 7.17nH 9.94pF
…
Input driver I(V)
characteristics
file
Output driver I(V)
characteristics
Very important for :
 I/O switching noise prediction
 I/O immunity prediction
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July 15
Test bench model
Test bench model
 Electrical model extracted by S parameter measurements and electromagnetic
simulations
 Test bench models should be generic
 Limited frequency range due to influence of parasitic elements, apparition of
high order propagation mode
DUT
C=20fF
R=1Ω L=4nH
K=1%
C=1nF
R=15mΩ
K=6%
L=0.5nH
TEM
TEM Cell
DPI capacitance
DPI injection
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July 15
DUT
Near-field scan
Emission measurement/simulation
Conducted/Radiated emission prediction
Simulations
Board
Model
Core
Model
Measurements
Elec. package
Model
DUT
1
IC Model
Time Domain
Simulation
To receiver
Spectrum
analyzer
FFT of Vanalyzer(t)
EMC model
Compare spectrums
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July 15
Measurements
Emission measurement/simulation
Conducted/Radiated emission prediction
Emission
spectrum
dBµV
measurement
simulation
ICEM model
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July 15
MHz
Emission measurement/simulation
Near field method - theory


H P    H i
H1
i
P
H2
Vss
I(vss)
chip
H
Vdd
r
I(vdd)
P
L I
Magnetic near field scan of a 16
bit microcontroller
 Package is the main contributor of the radiated emission of an IC
 Magnetic field emission is generated by the flowing of parasitic current
through package pins
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July 15
Emission measurement/simulation
Near field method – prediction principle
Scan Simulations
VssX1
Scan Measurements
VssA
Vdd1
Vss1
Vss2
Vdd2
VssX2
VssR2
VssR1 VddR1
Core
Model
Elec. package
Model
Geometrical
package model
Spectrum
analyser
Analog Time Domain
Simulation
Positionning
[x,y]
H[x,y] at given f,
given z
Fourier Transform of I(t)
H[x,y,z] of I(f)
Compare scans
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July 15
Emission measurement/simulation
Near-field scan: S12X case study (144 pins, 0.25µm)
Package model
with 13 leads
Scan area
Simulation of H field at
Measurement of H field
32 MHz
at 32 MHz
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July 15
Susceptibility measurement/simulation
Susceptibility prediction model
IBIS
Amplitude
ICEM
Coupling
path model
Vdd
input
Time
clock
Functional
model
output
Resonance
Vss
Disturbance model
I/O
Supply network Z(f)
IC model
 ICIM draft standard (Integrated Circuit immunity Model)
 Reuse of standard non-confidential models (ICEM, IBIS)
 Susceptibility peaks linked with supply network anti-resonances
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July 15
Susceptibility measurement/simulation
Susceptibility simulation flow
Aggressed IC
Model (ICEM)
IC-EMC
Package
and IO model (IBIS)
RFI and coupling
path model (Z(f))
Set RFI frequency
Increase V aggressor
WinSPICE
Increase RFI
frequency
Time domain simulation
Susceptibility threshold
simulation
Criterion analysis
IC-EMC
Extract forward power
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July 15
Susceptibility measurement/simulation
16 bit micro-controller I/O susceptibility prediction
•
•
•
•
•
16 bit micro-controller
Direct power injection
Input buffer aggression
Sinusoidal mode
Simulation criterion:
Logical change of input
buffer
From A. Boyer’s
PhD, INSA, 2007
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July 15
Conclusion
•
EMC models can help earn/save money
•
Macro-models of ICs include core, I/O and package modeling
•
The core model is based on current evaluation and on-chip
capacitance
•
The package model is based on RLC
•
Good prediction of emission and susceptibility up to 2 GHz
•
Soon, requirements up to 3-10 GHz
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July 15