Transcript Binary Counters

Binary Counters
Module M10.3
Section 7.2
Counters
• 3-Bit Up Counter
• 3-Bit Down Counter
• Up-Down Counter
Divide-by-8 Counter
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
s0
s1
s2
s3
s4
s5
s6
s7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
Q0.D
D
CLK
Q1.D
D
CLK
Q2.D
D
CLK
Q
Q0
!Q
Q
Q1
!Q
Q
!Q
Q2
Divide-by-8 Counter
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
s0
s1
s2
s3
s4
s5
s6
s7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
Q1 Q0
00
Q2
01
11
1
0
1
10
1
1
1
Q2.D
Q2.D = !Q2 & Q1 & Q0
# Q2 & !Q1
# Q2 & !Q0
Divide-by-8 Counter
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
s0
s1
s2
s3
s4
s5
s6
s7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
Q1 Q0
00
Q2
01
11
10
0
1
1
1
1
1
Q1.D
Q1.D = !Q1 & Q0
# Q1 & !Q0
Divide-by-8 Counter
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
s0
s1
s2
s3
s4
s5
s6
s7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
Q1 Q0
00
Q2
01
11
10
0
1
1
1
1
1
Q0.D
Q0.D = ! Q0
div8cnt.abl
MODULE Div8Cnt
TITLE 'Divide by 8 Counter, D. Hanna, 7/20/02'
DECLARATIONS
" INPUT PINS "
PB PIN 10;
" push-button switch (clock)
" OUTPUT PINS "
Q2..Q0 PIN 37,36,35 ISTYPE 'reg buffer';
Q = [Q2..Q0];
" LED 6..8
" 3-bit output vector
[A,B,C,D,E,F,G,DP] PIN 15,18,23,21,19,14,17,24 ISTYPE 'com';
Segments = [A,B,C,D,E,F,G];
" 7-segment LED display
EQUATIONS
Q.c = PB;
Q2.d =
Q1.d =
Clock
div8cnt.abl (cont’d)
!Q2 & Q1 & Q0
# Q2 & !Q1
# Q2 & !Q0;
!Q1 & Q0 # Q1 & !Q0;
Q0.d = !Q0;
DP = PB;
@radix 16;
truth_table ( Q -> Segments )
0 -> 7E;
1
2
3
4
5
6
7
END
->
->
->
->
30;
6D;
79;
33;
-> 5B;
-> 5F;
-> 70;
Div8Cnt
" decimal point
" 7-segment display
Simulation File, div8cnt.si
Listing 7.4
Name
Partno
Revision
Date
Designer
Company
Location
Assembly
Device
Format
div8cnt.si
div8cnt;
OU0023;
01;
8/05/91;
R. E. Haskell;
Oakland University;
Rochester, MI;
CSE 171;
G16V8;
j;
CUPL Simulation
File
/********************************************************/
/*
*/
/*
This example demonstrates the use of D-type
*/
/*
flip-flops to design a divide-by-8 counter
*/
/*
*/
/********************************************************/
/*
Target Device: G16V8
*/
/********************************************************/
div8cnt.si
ORDER:
VECTORS:
C LLL
C HLL
C LHL
C HHL
C LLH
C HLH
C LHH
C HHH
C LLL
C HLL
C LHL
C HHL
C LLH
C HLH
C LHH
C HHH
clock,%2,q0,%2,q1,%2,q2;
CUPL Simulation
File
CUPL Simulation
Output File
Counters
• 3-Bit Up Counter
• 3-Bit Down Counter
• Up-Down Counter
3-Bit Down Counter
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
s0
s1
s2
s3
s4
s5
s6
s7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
Q0.D
D
CLK
Q1.D
D
CLK
Q2.D
D
CLK
Q
Q0
!Q
Q
Q1
!Q
Q
!Q
Q2
3-Bit Down Counter
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
s0
s1
s2
s3
s4
s5
s6
s7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
Q1 Q0
00
Q2
0
1
01
11
10
1
1
1
1
Q2.D
Q2.D = !Q2 & !Q1 & !Q0
# Q2 & Q1
# Q2 & Q0
3-Bit Down Counter
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
s0
s1
s2
s3
s4
s5
s6
s7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
Q1 Q0
00
Q2
01
11
0
1
1
1
1
1
Q1.D
Q1.D = !Q1 & !Q0
# Q1 & Q0
10
3-Bit Down Counter
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
s0
s1
s2
s3
s4
s5
s6
s7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
Q1 Q0
00
Q2
01
11
10
0
1
1
1
1
1
Q0.D
Q0.D = ! Q0
Counters
• 3-Bit Up Counter
• 3-Bit Down Counter
• Up-Down Counter
Up-Down Counter
clock
UD
Q0
Up-Down
Counter
UD = 0: count up
UD = 1: count down
Q1
Q2
Up-Down Counter
UD Q2 Q1 Q0 Q2.D Q1.D Q0.D
UD Q2 Q1
Q0 Q2.D Q1.D Q0.D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
0
Up-Counter
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
0
0
0
1
1
1
Down-Counter
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
Up-Down Counter
Q1 Q0
UD Q2
00
01
11
10
00
01
11
10
Make Karnaugh maps for Q2.D, Q1.D, and Q0.D