Transcript WinCupl - Computer Science and Engineering at Oakland

WinCupl
Module M2.2
Section 4.2
Experiment 2
X
Y
2
19
18
3
17
16
15
14
13
12
GAL 16V8
!(X $ Y)
X$Y
!(X # Y)
X#Y
!(X & Y)
X&Y
!Y
!X
Listing 4.1
exp2.pld
Name
Partno
Revision
Date
Designer
Company
Location
Assembly
Device
Format
Exp2;
OU0001;
04;
7/17/91;
R. E. Haskell;
Oakland University;
Rochester, MI;
CSE 171;
G16V8;
j;
/****************************************************************/
/*
*/
/*
This is an example to demonstrate how CUPL
*/
/*
compiles simple gates.
*/
/*
*/
/****************************************************************/
/*
Target Device: G16V8
*/
/****************************************************************/
/* Inputs:
Pin 2 =
Pin 3 =
define inputs to simple gates */
x;
y;
/* Outputs:
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
12
13
14
15
16
17
18
19
=
=
=
=
=
=
=
=
invx;
invy;
and;
nand;
or;
nor;
xor;
xnor;
/* Logic:
invx
invy
and
nand
or
nor
xor
xnor
=
=
=
=
=
=
=
=
define outputs as active HI levels */
!x;
!y;
x &
!(x
x #
!(x
x $
!(x
examples of simple gates expressed in CUPL */
/* inverters */
y;
& y);
y;
# y);
y;
$ y);
/*
/*
/*
/*
/*
/*
and gate */
nand gate */
or gate */
nor gate */
exclusive or gate */
exclusive nor gate */
CUPL Header
Name
Partno
Revision
Date
Designer
Company
Location
Assembly
Device
Format
Exp2;
OU0001;
04;
7/17/91;
R. E. Haskell;
Oakland University;
Rochester, MI;
CSE 171;
G16V8;
j;
CUPL Comments
/****************************************************************/
/*
*/
/*
This is an example to demonstrate how CUPL
*/
/*
compiles simple gates.
*/
/*
*/
/****************************************************************/
/*
Target Device: G16V8
*/
/****************************************************************/
CUPL Inputs and Outputs
/* Inputs:
Pin 2 =
Pin 3 =
x;
y;
/* Outputs:
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
12
13
14
15
16
17
18
19
=
=
=
=
=
=
=
=
define inputs to simple gates */
define outputs as active HI levels */
invx;
invy;
and;
nand;
or;
nor;
xor;
xnor;
CUPL Logic Equations
/* Logic:
invx
invy
and
nand
or
nor
xor
xnor
=
=
=
=
=
=
=
=
!x;
!y;
x &
!(x
x #
!(x
x $
!(x
examples of simple gates expressed in CUPL */
/* inverters */
y;
& y);
y;
# y);
y;
$ y);
/*
/*
/*
/*
/*
/*
and gate */
nand gate */
or gate */
nor gate */
exclusive or gate */
exclusive nor gate */
Running WinCupl
CUPL Chip Diagram
in .DOC File
______________
|
Exp2
|
x---|1
20|---x
x x---|2
19|---x
y x---|3
18|---x
x---|4
17|---x
x---|5
16|---x
x---|6
15|---x
x---|7
14|---x
x---|8
13|---x
x---|9
12|---x
GND x---|10
11|---x
|______________|
Vcc
xnor
xor
nor
or
nand
and
invy
invx
JEDEC File
CUPL
4.0a Serial# MD-40A-7985
Device
g16v8s Library DLIB-h-26-9
Created
Thu Jul 18 13:27:16 1991
Name
Exp2
Partno
OU0001
Revision
04
Date
7/17/91
Designer
R. E. Haskell
Company
Oakland University
Assembly
CSE 171
Location
Rochester, MI
*QP20
*QF2194
*G0
*F0
*L00000 01111011111111111111111111111111
*L00032 10110111111111111111111111111111
*L00256 01111011111111111111111111111111
*L00288 10110111111111111111111111111111
*L00512 01111111111111111111111111111111
*L00544 11110111111111111111111111111111
*L00768 01111111111111111111111111111111
*L00800 11110111111111111111111111111111
*L01024 01110111111111111111111111111111
*L01280 01110111111111111111111111111111
*L01536 11111011111111111111111111111111
*L01792 10111111111111111111111111111111
*L02048 01010111100011000000110000001100
*L02080 00001100101010101111001000000000
*L02112 00000000000000001111111111111111
*L02144 11111111111111111111111111111111
*L02176 111111111111111110
*C394C
* DB34
JEDEC File Header
CUPL
Device
Created
Name
Partno
Revision
Date
Designer
Company
Assembly
Location
*QP20
*QF2194
*G0
*F0
4.0a Serial# MD-40A-7985
g16v8s Library DLIB-h-26-9
Thu Jul 18 13:27:16 1991
Exp2
OU0001
04
7/17/91
R. E. Haskell
Oakland University
CSE 171
Rochester, MI
JEDEC File Fuse Map
*L00000
*L00032
*L00256
*L00288
*L00512
*L00544
*L00768
*L00800
*L01024
*L01280
*L01536
*L01792
*L02048
*L02080
*L02112
*L02144
*L02176
*C394C
* DB34
01111011111111111111111111111111
10110111111111111111111111111111
01111011111111111111111111111111
10110111111111111111111111111111
01111111111111111111111111111111
11110111111111111111111111111111
01111111111111111111111111111111
11110111111111111111111111111111
01110111111111111111111111111111
01110111111111111111111111111111
11111011111111111111111111111111
10111111111111111111111111111111
01010111100011000000110000001100
00001100101010101111001000000000
00000000000000001111111111111111
11111111111111111111111111111111
111111111111111110
Simulator
•
•
•
•
Copy Exp2.pld to Exp2.si
Delete everything after the header
Add ORDER statement
Add test VECTORS
Copy this header EXACTLY
from the file exp2.pld and copy
to the file exp2.si
Name
PartNo
Date
Revision
Designer
Company
Assembly
Location
Device
Exp2;
OU0001;
7/17/91;
04;
R. E. Haskell;
Oakland University;
CSE 171;
Rochester, MI;
G16V8;
/****************************************************************/
/*
*/
/*
This is an example to demonstrate how CUPL
*/
/*
compiles simple gates.
*/
/*
*/
/****************************************************************/
/*
Taget Device: G16V8
*/
/****************************************************************/
Add the following to the file exp2.si
ORDER: x, %2, y, %4, invx, %2, invy, %2, and, %2, nand, %2,
or, %2, nor, %2, xor, %2, xnor;
VECTORS:
00 HHLHLHLH
01 HLLHHLHL
10 LHLHHLHL
11 LLHLHLLH
ORDER statement
Test vectors
ORDER Statement
ORDER: x, %2, y, %4, invx, %2, invy, %2, and, %2, nand, %2,
Inputs:
0, 1
01 HLLHHLHL
Test Vector
Outputs:
L, H
%2 means “leave 2 spaces when printing
simulation results”
Test Vectors
VECTORS:
00 HHLHLHLH
01 HLLHHLHL
10 LHLHHLHL
11 LLHLHLLH
The 4 test vectors represent
the 4 rows in the truth table.
WinCupl Demo