Transcript Shift Registers

Shift Registers
Module M11.1
Section 7.3
4-Bit Shift Register
data_in
CLK
Q0
Q1
Q2
Q3
shift4.abl
MODULE Shift4
TITLE '4-bit Shift Register A. Student, 7/22/02'
DECLARATIONS
" INPUT PINS "
PB PIN 10;
" push-button switch (clock)
Clear PIN 7;
" Switch 2
Load PIN 11;
" Switch 3
data_in PIN 70;
" Switch 8
" OUTPUT PINS "
Q3..Q0 PIN 39,37,36,35 ISTYPE 'reg buffer';
Q = [Q3..Q0];
" LED 5..8
" 3-bit output vector
shift4.abl (cont’d)
EQUATIONS
Q.c = PB;
Q0.d =
!Clear & data_in;
Q1.d =
!Clear & Q0;
Q2.d =
!Clear & Q1;
Q3.d =
!Clear & Q2;
END Shift4
data_in
CLK
Q0
Q1
Q2
Q3
4shift.si
Listing 7.12
Name
Partno
Revision
Date
Designer
Company
Location
Assembly
Device
Format
CUPL Simulation
File
4shift.si
4shift;
OU0031;
01;
8/07/91;
R. E. Haskell;
Oakland University;
Rochester, MI;
CSE 171;
G16V8;
j;
/********************************************************/
/*
This is a 4-bit shift register
*/
/********************************************************/
/*
Target Device: G16V8
*/
/********************************************************/
4shift.si
ORDER:
CUPL Simulation
File
clock,%2,clear,%2,data_in,%2,q0,%2,q1,%2,q2,%2,q3;
VECTORS:
C10 LLLL
C01 HLLL
C00 LHLL
C00 LLHL
C00 LLLH
C00 LLLL
C01 HLLL
C00 LHLL
C01 HLHL
C00 LHLH
C01 HLHL
C00 LHLH
C00 LLHL
C00 LLLH
C00 LLLL
/* clear register */
CUPL Simulation
Output File
Ring Counter
Q0
CLK
Q1
Q2
Q3
ring4.abl
MODULE Ring4
TITLE '4-bit Ring Counter A. Student, 7/22/02'
DECLARATIONS
" INPUT PINS "
PB PIN 10;
" push-button switch (clock)
Clear PIN 7;
" Switch 2
" OUTPUT PINS "
Q3..Q0 PIN 39,37,36,35 ISTYPE 'reg buffer';
Q = [Q3..Q0];
" LED 5..8
" 3-bit output vector
ring4.abl (cont’d)
EQUATIONS
Q.c = PB;
Q0.d =
!Clear & Q3;
Q1.d =
!Clear & Q0;
Q2.d =
!Clear & Q1;
Q3.d =
!Clear & Q2 # Clear;
END Ring4
Q0
CLK
Q1
Q2
Q3
ring4.si
Listing 7.14
Name
Partno
Revision
Date
Designer
Company
Location
Assembly
Device
Format
CUPL Simulation
File
ring4.si
ring4;
OU0032;
01;
8/07/91;
R. E. Haskell;
Oakland University;
Rochester, MI;
CSE 171;
G16V8;
j;
/********************************************************/
/*
This is a 4-bit ring counter
*/
/********************************************************/
/*
Target Device: G16V8
*/
/********************************************************/
ring4.si
ORDER:
CUPL Simulation
File
clock,%2,clear,%2,q0,%2,q1,%2,q2,%2,q3;
VECTORS:
C1 LLLH
C0 HLLL
C0 LHLL
C0 LLHL
C0 LLLH
C0 HLLL
C0 LHLL
C0 LLHL
C0 LLLH
C0 HLLL
C0 LHLL
C0 LLHL
C0 LLLH
C0 HLLL
C0 LHLL
C0 LLHL
C0 LLLH
CUPL Simulation
Output File
Ring Counter
Q0
CLK
Q1
Q2
Q3
Johnson Counter
Exercise
Detect input sequence 1101
din
clk
fsm
dout
clr
din
dout
1 0 1 1 0 1 1 0 1 0 0 1 1 0 1 0
0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0
Use Shift Register
dout
1
din
D
CLK
CLK
Q
!Q
Q0
0
D
CLK
Q
!Q
Q1
1
D
CLK
Q
!Q
Q2
1
D
CLK
Q
!Q
Q3
Lab 8
Johnson Counter & Random
Number Generator
D
CLK
Q
!Q
Q3
D
CLK
Q
!Q
Q2
D
CLK
CLK
Random Number Generator
Q
!Q
Q1
D
CLK
Q
!Q
Q0
Q3
D
Q
Q2
D
CLK !Q
Q
Q1
D
CLK !Q
Q0
Q
D
CLK !Q
Q
CLK !Q
CLK
Q3 Q2 Q1 Q0
0
1
1
1
1
0
1
0
0
0
1
1
1
1
0
1
0
0
0
1
1
1
1
0
1
0
0
0
1
1
1
1
Q3 Q2 Q1 Q0
1
8
C
E
F
7
B
5
1
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
1
0
1
1
0
0
1
0
0
1
0
1
1
0
0
1
A
D
6
3
9
4
2
1