Transcript Shift Registers

Shift Registers
Lecture L8.6
Section 8.3
4-Bit Shift Register
data_in
Q3
D
CLK
CLK
Q
!Q
Q2
D
CLK
Q
!Q
Q1
D
CLK
Q
!Q
Q0
D
CLK
Q
!Q
shift4.abl
MODULE shift4
TITLE '4-bit Shift Register'
DECLARATIONS
" INPUT PINS "
CLK PIN 70;
clear PIN 11;
data_in PIN 1;
" push-button switch (clock)
" Switch S6:1
" Switch S7:4
" OUTPUT PINS "
Q3..Q0 PIN 40,41,43,44 ISTYPE 'reg buffer'; " LED 13..16
Q = [Q3..Q0];
" 4-bit output vector
shift4.abl (cont’d)
EQUATIONS
Q.AR = clear;
Q.C = CLK;
Q3.D = data_in;
Q2.D = Q3;
Q1.D = Q2;
Q0.D = Q1;
data_in
Q3
D
CLK
CLK
Q
!Q
Q2
D
CLK
Q
!Q
Q1
D
CLK
Q
!Q
Q0
D
CLK
Q
!Q
shift4.abl (cont’d)
@radix 16;
test_vectors([CLK, clear, data_in] -> Q)
[.C.,1,0] -> 0;
[.C.,0,1] -> 8;
[.C.,0,0] -> 4;
[.C.,0,0] -> 2;
[.C.,0,0] -> 1;
[.C.,0,0] -> 0;
[.C.,0,1] -> 8;
[.C.,0,0] -> 4;
[.C.,0,1] -> 0A;
[.C.,0,0] -> 5;
[.C.,0,1] -> 0A;
[.C.,0,0] -> 5;
[.C.,0,0] -> 2;
[.C.,0,0] -> 1;
[.C.,0,0] -> 0;
END
shift4 simulation
Ring Counter
Q3
D
CLK
CLK
Q
!Q
Q2
D
CLK
Q
!Q
Q1
D
CLK
Q
!Q
Q0
D
CLK
Q
!Q
ring4.abl
MODULE ring4
TITLE '4-bit Ring Counter'
DECLARATIONS
" INPUT PINS "
CLK PIN 70;
start PIN 11;
" push-button switch (clock)
" Switch S6:1
" OUTPUT PINS "
Q3..Q0 PIN 40,41,43,44 ISTYPE 'reg buffer'; " LED 13..16
Q = [Q3..Q0];
" 4-bit output vector
Q31 = [Q3..Q1];
" upper 3 bits
ring4.abl (cont’d)
EQUATIONS
Q31.AR = start;
Q0.AP = start;
Q.C = CLK;
Q3.D
Q2.D
Q1.D
Q0.D
=
=
=
=
" asynchronous reset
" asynchronous preset
start = 1
Q0;
Q3;
Q2;
Q1;
0
0
Q3
D
CLK
CLK
Q
!Q
0
Q2
D
CLK
Q
!Q
1
Q1
D
CLK
Q
!Q
Q0
D
CLK
Q
!Q
ring4.abl (cont’d)
@radix 16;
test_vectors([CLK, start] -> Q)
[.C.,1] -> 1;
[.C.,0] -> 8;
[.C.,0] -> 4;
[.C.,0] -> 2;
[.C.,0] -> 1;
[.C.,0] -> 8;
[.C.,0] -> 4;
[.C.,0] -> 2;
[.C.,0] -> 1;
[.C.,0] -> 8;
[.C.,0] -> 4;
[.C.,0] -> 2;
[.C.,0] -> 1;
END
ring4 simulation
Ring Counter
Q3
D
CLK
CLK
Q
!Q
Q2
D
CLK
Q
!Q
Q1
D
CLK
Q
!Q
Q0
D
CLK
Q
!Q
Johnson Counter
Exercise
Detect input sequence 1101
din
clk
fsm
dout
clr
din
dout
1 0 1 1 0 1 1 0 1 0 0 1 1 0 1 0
0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0
Use Shift Register
dout
1
din
D
CLK
CLK
Q
!Q
Q3
0
D
CLK
Q
!Q
Q2
1
D
CLK
Q
!Q
Q1
1
D
CLK
Q
!Q
Q0
A Random Number Generator
Q3
D
Q
CLK !Q
CLK
Q2
D
Q
CLK !Q
Q1
D
Q
CLK !Q
Q0
D
Q
CLK !Q
Q3
D
Q
Q2
D
CLK !Q
Q
Q1
D
CLK !Q
Q0
Q
D
CLK !Q
Q
CLK !Q
CLK
Q3 Q2 Q1 Q0
0
1
1
1
1
0
1
0
0
0
1
1
1
1
0
1
0
0
0
1
1
1
1
0
1
0
0
0
1
1
1
1
Q3 Q2 Q1 Q0
1
8
C
E
F
7
B
5
1
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
1
0
1
1
0
0
1
0
0
1
0
1
1
0
0
1
A
D
6
3
9
4
2
1