Transcript Lab 7 - Computer Science and Engineering at Oakland University

Pulse-Width Modulated DAC
Lecture 11.3
Section 11.5
8-Bit Counter
1
CLK
Q0
count
Q1
div16cnt
Q3
clear
Q7
Q2
set = cnt2.Cout
Cout
pwm
SW
period
count
div16cnt
clear
Q4
Q5
Q6
Q7
Cout
reset = (Q == SW)
Pulse-Width Modulation
Q7
set = cnt2.Cout
pwm
SW
period
reset = (Q == SW)
Vpwm
reset
P
set
!P
SW

Vref
period
pwm
MODULE pwm
" pulse-width modulated signal “
DECLARATIONS
"Functional Blocks "
div16cnt interface ([CLK,clear,count] -> [Q3,Q2,Q1,Q0,Cout]);
cnt1 FUNCTIONAL_BLOCK div16cnt;
cnt2 FUNCTIONAL_BLOCK div16cnt;
" Input Pins "
Clock PIN 9;
SW7..SW0 PIN 11,7,6,5,4,3,2,1;
SW = [SW7..SW0];
" 4 MHz clock
" Switches 1..8
" 8-bit high tim
" Output Pins "
LED9 PIN 35 ISTYPE 'com';
LED10 PIN 36 ISTYPE 'com';
" PWM output -- LED9
" !PWM output -- LED10
" Intermediate Nodes "
Q7..Q0 NODE ISTYPE 'com';
Q = [Q7..Q0];
" Clock divider
P NODE ISTYPE 'com';
notP NODE ISTYPE 'com';
set NODE ISTYPE 'com';
" Definitions "
reset = (Q == SW);
" equality detector
reset
P
set
!P
pwm
EQUATIONS
cnt1.clear
cnt2.clear
cnt1.CLK =
cnt2.CLK =
cnt1.count
cnt2.count
= 0;
= 0;
Clock;
Clock;
= 1;
= cnt1.Cout;
" Clock divider
[Q7..Q4] = cnt2.[Q3..Q0];
[Q3..Q0] = cnt1.[Q3..Q0];
set = cnt2.Cout;
P = !(reset # notP);
notP = !(set # P);
" set every Q7 period
" S-R latch
LED9 = P;
LED10 = notP;
reset
P
set
!P
END pwm
pwm