EE2174: Digital Logic and Lab

Professor Shiyan Hu Department of Electrical and Computer Engineering Michigan Technological University

CHAPTER 1 Introduction

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Class Time and Office Hour

    Class Time: MWF 08:05-08:55 (EERC 214) and 12:05-12:55 (EERC 103) Office Hours: MWF 09:00-10:00, 13:00-14:00 or by appointment, office: EERC 518 Textbook (required): Digital Design, fourth edition, by John Wakerly , Prentice Hall, 2006. Grading:     Homework/Quiz 25% Midterm 20% Final 30% Lab 25%

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Course Website

  http://www.ece.mtu.edu/faculty/shiyan/EE2174Fall14.htm Contact information of instructor  Email: [email protected]

  EERC 518 Instructor’s webpage: http://www.ece.mtu.edu/faculty/shiyan

Textbook and Lab

• • • • Digital Design: Principles and Practices, John F. Wakerly Pearson Prentice Hall, 2006 0-13-186389-4 Quartus II software in labs

Grades and Grading

• Your grade will be comprised of:  Homework/quiz 25%    Midterm 20% Final 30% Lab 25% • Grade scale: • 90 – 100% - A • • • • 85 – 90% - AB 80– 85% - B 75 – 80% - BC 70 – 75% - C • • • 65 – 70% - CD 60 – 65% - D < 60% - F

A Few Notes on Grading

• • • You cannot pass this class by simply taking the exams. You have to do the homework and take the quizzes or you will not pass.

• Don’t stress out about the midterms.

They don’t affect your grade that much.

It is very hard to answer the question, “How am I doing in this class?” • Simply showing up is not going to get you a good grade. You will earn your grade.

Late Assignment Policy

• • • All assignments are expected to be turned in during class on the due date unless otherwise noted.

• If an assignment is turned in after that time, I will accept it and assign a 25% penalty for each 24-hour period it is late.

Examples: Mike turns his assignment in at 8 AM the day after the due date. He loses 25%. George turns his in at 3 PM the next day. He loses 50%. • This will be calculated by simply multiplying your earned score by the appropriate penalty. Consider that Mike earned 30/40 points on his assignment. After his 25% late penalty, he would receive a final score of 23/40 (rounded up).

Weekend days count as days too. An assignment due on Friday that is turned in on Monday is subject to a 50% penalty.

• If the solutions to an assignment are posted prior to the normal expiration of this period (to facilitate studying for an exam, for example), assignments will no longer be accepted.

Homework

• • • • • You will have at least 8 sets of homework.

The point is to give you practical experience with what you’re learning.

No problem if you want to work together.

You need to write down your own solution.

You need to credit anybody you work with!

Homework

• Homework assignments will be posted. All homework questions will be graded for correctness. Questions will come both from the textbook as well as created by the instructor.

• Solutions for homework assignments will be posted after the expiration of the grace period.

• Quiz solutions will be discussed in class and will only be posted online if they cannot be discussed before an exam. • Exam solutions will only be discussed in class.

A Few Hints for Success

• • • • Come to class.

Do the homework.

Do the lab.

Please come to see me.

What is this course all about?

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Introduction to digital logic.

 Digital system fundamentals, number system, digital circuit, combinational logic and sequential logic.

What will you learn?

 Understanding and designing digital logic circuits with respect to different quality metrics such as functionality, timing, power and area.

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Agenda

       Introduction Number system Digital circuit Combinational logic Sequential logic Design methodologies VLSI Computer-Aided Design

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Why is this course important?

2000 42 million transistors 1.5 GHz

The base for modern circuit design

Many Chips

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Moore’s Law

 In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.

Moore’s law

Twice the number of transistors, approximately every two years

Moore’s Law

16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

18 Electronics, April 19, 1965.

ITRS Prediction

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Course Mission

• This course is intended to provide you with an understanding of logic design theory and practice and with the skills to design simple circuits manually and complex circuits with software.

Chapter 1 Overview

  Analog v.s. Digital Digital system is everywhere 28-Apr-20 Chapter 1: Digital Computers and Information PJF - 21

Analog vs. Digital

• Analog signals can take any value across a continuous range of current, voltage, etc.

• • Digital circuits They just don’t.

• They restrict themselves to two discrete values of 0 and 1, low and high, false and true.

Once Analog, Now Digital

• • • • • • Still pictures Video recordings Audio recordings Telephone systems Traffic Lights And so on…

Why Digital?

• • • • • • • Reproducibility of results Ease of design Flexibility and functionality Programmability Speed Economy Steadily advancing technology

Simple Digital Circuits

• • Logic Gates AND OR NOT • • Flip-flops • Sequential Circuits Counters, Registers, State Machines

Designing Digital Circuits

• • Old Days: Designed by hands • Today: Using CAD tools Schematic entry • • • • • • Hardware Description Languages HDL text editors, compilers and synthesizers Simulators Test Benches Timing Analyzers Word processors

Integrated Circuits

• • • Lots of gates on a chip are called Integrated Circuits.

Initially part of a wafer, then sliced and diced up.

• Classified by scale of integration: 1-20 Gates: Small Scale Integration • • • 20-200 Gates: Medium Scale Integration 200-1,000,000 Gates: Large Scale Integration > 1,000,000 Gates: Very Large Scale Integration (VLSI)

Three types of ICs

   Full custom design Cell library based design Programmable logic array based design 28-Apr-20 Chapter 1: Digital Computers and Information PJF - 28

Full Custom Design

• • • Full Custom Design More commonly called “ASIC” (Application Specific IC) Faster, because they’re designed with a purpose • • Design time is huge though Unisys took 3-4 years to design a processor

Programmable Logic Array

• • • • Programmable Logic Device • Very popular today because Short development cycle • Easy to fix broken design Reprogrammable FPGA (field programmable gate array) is a common, but sophisticated PLD

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Important Themes of Digital System

Understand and use standard functional building blocks.

State-machine design is like programming; approach it that way.

Design for minimum cost at the system level, including your own engineering effort as part of the cost.

Design for testability and manufacturability.

Use programmable logic to simplify designs, reduce cost and accommodate last-minute modifications.

Practice synchronous design until a better methodology comes along (if ever).

Summary

• • Digital design is ubiquitous and pervasive. There is a lot to talk about the digital system.